Digital Signal Processing Reference
In-Depth Information
Mode:
A direction of signal (either in, out, inout or buffer) used as subprogram
parameter or port.
Model:
A representation that behaves similarly to the operation of some digital
circuit.
MPLD:
Acronym for Mask Programmed Logic Device.
Netlist:
A text file that describes a logic design. Minimal requirements are
identification of function elements, inputs, outputs, and connections.
Netist synthesis:
Process of deriving a netlist from an abstract representation, usually
from a hardware description language.
Nios:
A soft core RISC processor supported on Altera FPGAs.
NRE:
Acronym for Non-Recurring Engineering expense. It reefers to one-time charge
covering the use of design facilities, masks and overhead for test development of
ASICs.
Object:
A named entity of a specific type that can be assigned a value. Object in
VHDL include signals, constants, variables and files.
Octal:
The base 8 number system (radix). Octal digits are 0 though 7.
One Hot Encoding:
A design technique used more with FPGAs than CPLDs. Only
one flip-flop output is active at any time. One flip-flop per state is used. State outputs
do not need to be decoded and they are hazard free.
Package:
A collection of commonly used VHDL constructs that can be shared by
more than one design unit.
PAL:
Acronym for programmable array logic. A relatively small FPLD containing a
programmable AND plane followed by a fixed-OR plane.
Parameter:
An object or literal passed into a subprogram via that subprogram's
parameter list.
Partitioning:
Setting boundaries between subsections of a system or between multiple
FPGA devices.
Physical types:
A data type used to represent measurements.
Pin Number:
A number used to assign an input or output signal in a design file,
which corresponds to the pin number on an actual device.
PLA:
(programmable logic array) a relatively small FPLD that contains two levels of
programmable logic-an AND plane and an OR plane.
PLL:
(phase locked loop) a device that can be used to multiply and divide clock
signals and adjust the phase delay.
Placement:
Physical assignment of a logical function to a specific location within an
FPGA. Once the logic function is placed, its interconnection is made by routing.
PLD:
Acronym for programmable logic device. This class of devices is comprised of
PALs, PLAs, FPGAs, and CPLDs.
Port:
A symbolic name that represents an input or output of a primitive or of a
macrofunction design file.
Primitive:
One of the basic functional blocks used to design circuits with Quartus II
software. Primitives include buffers, flip-flops, latch, logical operators, ports, etc.
Process:
A basic VHDL concurrent statement represented by a collection of
sequential statements that are executed whenever there is an event on any signal that
appears in the process sensitivity list, or whenever an event occurs that satisfies
condition of a wait statement within the process.
