Glossary - Rapid Prototyping of Digital Systems - page 406

State transition diagram: A graphical representation of the operation of a finite state
machine using directed graphs.
State: A state is implemented in a device as a pattern of 1's and 0's (bits) that are the
outputs of multiple flip-flops (collectively called a state machine state register).
Structural-type architecture: The level at which VHDL describes a circuit as an
arrangement of interconnected components.
Subprogram: A function or procedure. It can be declared globally or locally.
Sum-of-products: A Boolean expression is said to be in sum-of-products form if it
consists of product terms combined with the OR operator.
Synthesis: The process of converting the model of a design described in VHDL from
one level of abstraction to another, lower and more detailed level that can be
implemented in hardware.
Test bench: A VHDL model used to verify the correct behavior of another VHDL
model, commonly known as the unit under test.
Tri-state Buffer: A buffer with an input, output, and controlling Output Enable
signal. If the Output Enable input is High, the output signal equals the input. If the
Output Enable input is Low, the output signal is in a state of high impedance . Tri-state
outputs can be tied together but only one should ever be enabled at any given time.
Timing Simulation: A simulation that includes the actual device delay times.
Two's Complement: A system of representing binary numbers in which the negative
of a number is equal to its logic inverse plus 1. In VHDL, you must declare a two's
complement binary number with a signed data type or use the signed library.
Type: A declared name and its corresponding set of declared values representing the
possible values the type.
Type declaration: A VHDL declaration statement that creates a new data type. A type
declaration must include a type name and a description of the entire set of possible
values for that type.
Universal logic cell: A logic cell capable of forming any combinational logic function
of the number of inputs to the cell. RAM, ROM and multiplexers have been used to
form universal logic cells. Sometimes they are also called look-up tables or function
generators.
Usable gates: Term used to denote the fact that not all gates on an FPGA may be
accessible and used for application purposes.
Variable: In VHDL, a data object that has only current value that can be changed in
variable assignment statement.
Verilog: An HDL with features similar to VHDL with a syntax reminiscent of C.
VCC: A high-level input voltage represented as a High (1) logic level in binary group
values.
VHDL: Acronym for VHSIC (Very High Speed Integrated Circuits) Hardware
Description Language. VHDL is used to describe function, interconnect and modeling.
VITAL: Acronym for VHDL Initiative Toward ASIC Libraries. An industry-standard
format for VHDL simulation libraries.