Digital Signal Processing Reference
In-Depth Information
Embedded Array Block (EAB):
A physically grouped set of 8 embedded cells that
implement memory (RAM or ROM) or combinatorial logic in a Cyclone 10K device.
A single EAB can implement a memory block of 256 x 8, 512 x 4, 1,024 x 2, or 2,048
x 1 bits.
EPLD:
Acronym for EPROM programmable logic devices. This is a PLD that uses
EPROM cells to internally configure the logic function. Also, erasable programmable
logic device.
Event:
The change of value of a signal. Usually refers to simulation.
Event scheduling:
The process of scheduling of signal values to occur at some
simulated time.
Excitation function:
A Boolean function that specifies logic that directs state
transitions in a state machine.
Exit condition:
An expression that specifies a condition under which a loop should be
terminated.
FLEX 10K and FLEX 10KA:
An Altera device family based on Flexible Logic
Element MatriX architecture. This SRAM-based family offers high-performance,
register-intensive, high-gate-count devices with embedded arrays. The Cyclone 10K
device family includes the EPF10K100, EPF10K70, EPF10K50, EPF10K40,
EPF10K30, EPF10K20, and EPF10K10 devices. The FPGA used on the UP2 board.
Fan-out:
The number of output signals that can be driven by the output of a logic cell.
Fast Track interconnect:
Dedicated connection paths that span the entire width and
height of a Cyclone device. These connection paths allow the signals to travel between
all LABs in device.
Field name:
An identifier that provides access to one element of a record data type.
File type:
A data type used to represent an arbitrary-length sequence of values of a
given type.
For loop:
A VHDL loop construct in which an iteration scheme is a for statement.
Finite state machine:
The model of a sequential circuit that cycles through a
predefined sequence of states.
Fitting:
Process of making a design fit into a specific FPGA architecture. Fitting
involves technology mapping, placement, optimization, and partitioning among other
operations.
Flash:
A non-volatile memory technology that also can be programmed in-circuit.
Flip-flop:
An edge-sensitive memory device (cell) that stores a single bit of data.
Floorplan:
Physical arrangement of functions within a connection framework of
signal routing channels.
FPGA:
Acronym for field programmable gate array. A regular array of logic cells that
is either functionally complete or universal with an interconnection network of signal
routing channels.
FPLD:
Acronym for field programmable logic device. An integrated circuit used for
implementing digital hardware that allows the end user to configure the chip to realize
different designs. Configuring such a device is done using either a special
programming unit or by doing it " in system". FLPDs include both CPLDs and
FPGAs.
Functional simulation
: A simulation mode that simulates the logical performance of
a project without timing information.
