Glossary - Rapid Prototyping of Digital Systems - page 400

Cell: A logic function. It may be a gate, a flip-flop, or some other structure. Usually, a
cell is small compared to other circuit building blocks.
Cell library: The collective name for a set of logic functions defined by the
manufacturer of an FPGA or ASIC. Simulation and synthesis tools use cell libraries
when simulating and synthesizing a model.
CLB: Acronym for Configurable Logic Block. This element is the basic building
block of the Xilinx FPGA product family.
Clock: A signal that triggers registers. In a flip-flop or state machine, the clock is an
edge-sensitive signal. In edge-triggered flip-flops, the output of the flip-flop can
change only on the clock edge.
Clock enable: The level-sensitive signal on a flip-flop with E suffix, e.g., DFFE.
When the Clock enable is low, clock transitions on the clock input of the flip-flop are
ignored.
Compiler Netlist File (.cnf): A binary file (with the extension .cnf) that contains the
data from a design file. The CNF is created by the Compiler Netlist Extractor module
of the MAX+PLUS II Compiler.
Component: Specifies the port of a primitive or macrofunction in VHDL. A
component consists of the name of the primitive or macrofunction, and a list of its
inputs and outputs. Components are specified in the Component declaration.
Component instantiation: A concurrent statement that references a declared
component and creates one unique instance of that component.
Configuration EPROM: A serial EPROM designed to configure (program) a FPGA.
Concurrent statements: HDL statements that are executed in parallel.
Configuration: It maps instances of VHDL components to design entities and
describes how design entities are combined to form a complete design. Configuration
declarations are used to specify which architectures to use for each entity.
Configuration scheme: The method used to load configuration (programming) data
into an FPGA.
Constant: An object that has a constant value and cannot be changed.
Control unit: The hardware of a machine that controls the data path.
Cyclone: The FPGA family used on the UP3 boards.
CPLD: Acronym for complex programmable logic device. CPLDs include an array of
functionally complete or universal logic cells with an interconnection network.
Data Path: The hardware path that provides data processing and transfer of
information in a machine, as opposed to the controller.
Design entity: A file that contains description of the logic for a project and is
compiled by the Compiler.
Design library: Stores VHDL units that have already been compiled. These units can
be referenced in VHDL designs.
Design unit: A section of VHDL description that can be compiled separately. Each
design unit must have a unique name within the project.
Dual-purpose pins: Pins used to configure an FPGA device that can be used as I/O
pins after initialization.
Dynamic reconfigurability: Capability of an FPGA to change its function "on -the-
fly"