Digital Signal Processing Reference
In-Depth Information
Glossary
Assignment & Configuration File (.acf):
An ASCII file (with the extension .acf)
used by the older MAX+PLUS tool to store information about probe, pin, location,
chip, clique, logic option, timing, connected pin and device assignments, as well as
configuration settings for the Compiler, Simulator, and Timing Analyzer for an entire
project. The ACF stores information entered with menu commands in all MAX+PLUS
II applications. You can also edit an ACF manually in a Text Editor window. This
same information is now found in the *.q* files in Quartus II.
Active-high (Active-low) node:
A node that is activated when it is assigned a value
one (zero) or Vcc (Gnd).
AHDL:
Acronym for Altera Hardware Description Language. Design entry language
that supports Boolean equation, state machine, conditional, and decode logic. It also
provides access to all Altera and user-defined macrofunctions.
Ancillary file:
A file that is associated with a Quartus II project, but is not a design
file in the project hierarchy tree.
Antifuse:
Any of the programmable interconnect technologies forming electrical
connection between two circuit points rather than making open connections.
Architecture:
Describes the behavior, RTL or dataflow, and/ or structure of a VHDL
entity. An architecture is created with an architecture body. A single entity can have
more than one architecture. In some VHDL tools, configuration declarations are used
to specify which architectures to use for each entity.
Array:
A collection of one or more elements of the same type that are accessed using
one or more indices depending on dimension of array. Array data types are declared
with an array range and array element type.
ASIC:
Acronym for Application-Specific Integrated Circuit. A circuit whose final
photographic mask process is user design dependent.
ASM:
Acronym for Algorithmic State Machine Chart. A flow-chart based method
used to represent a state diagram.
Assert:
A statement that checks whether a specified condition is true. If the condition
is not true, a report is generated during simulation.
Assignment:
In VHDL, assignment refers to the transfer of a value to a symbolic
name or group, usually through a Boolean equation. The value on the right side of an
assignment statement is assigned to the symbolic name or group on the left.
Asynchronous input:
An input signal that is not synchronized to the device Clock.
Attribute:
A special identifier used to return or specify information about a named
entity. Predefined attributes are prefixed with the ' character.
Back annotation:
Process of incorporating time delay values into a design netlist
reflecting the interconnect capacitance obtained from a completed design. Also, in
Altera's case, the process of copying device and resource assignments made by the
Compiler into the Assignment and Configuration File for a project. This process
preserves the current fit in future compilations.
Block:
A feature that allows partitioning of the design description within an
architecture.
Buried node:
A combinatorial or registered signal that does not drive an output pin.
