Digital Signal Processing Reference
In-Depth Information
Functional test vector:
The input stimulus used during simulation to verity a VHDL
model operates functionally as intended.
Functionally complete:
Property of some Boolean logic functions permitting them to
make any logic function by using only that function. The properties include making
the AND function with an invert or the OR function with an invert or the OR function
with an invert.
Fuse:
A metallic interconnect point that can be electrically changed from short circuit
to an open circuit by applying electrical current.
Gate:
An electronic structure, built from transistors that performs a basic logic
function.
Gate array:
Array of transistors interconnected to form gates. The gates in turn are
configured to form larger functions.
Gated clock:
A clock configuration in which the output of an AND or OR gate drives
a clock.
Generic:
A parameter passed to a VHDL entity, component or block that describes
additional, instance-specific information about that entity, component or block.
Glitch or spike:
A narrow output pulse that occurs when a logic level changes two or
more times over a short period.
Global signal:
A signal from a dedicated input pin that does not pass through the
logic array before performing its specified function. Clock, Preset, Clear, and Output
Enable signals can be global signals.
GND:
A Low-level input voltage. It is the default inactive node value.
Graphic Design File (.gdf):
A schematic design file (with the extension .gdf) created
with the MAX+PLUS II Graphic Editor.
HDL:
Acronym for Hardware Description Language. A special language used to
describe digital hardware.
Hexadecimal:
The base 16 number system (radix). Hexadecimal digits are 0 through 9
and A through F.
Hierarchy:
The structure of a design description, expressed as a tree of related
components.
Identifier:
A sequence of characters that uniquely identify a named entity in a design
description.
Index:
A scalar value that specifies an element or range of elements within an array.
Input vectors:
Time-ordered binary numbers representing input values sequences to a
simulation program.
I/O cell register:
A register on the periphery of a Cyclone 8000 device or a fast input-
type logic cell that is associated with an I/O pin.
IP core:
An intellectual property (IP) core is a previously developed synthesizable
hardware design that provides a widely used function. Commercially licensed IP cores
include functions such as microprocessors, microcontrollers, bus interfaces,
multimedia and DSP operations, and communications controllers.
LAB:
Acronym for Logic Array Block. The LAB is the basic building block of the
Altera MAX family. Each LAB contains at least one macrocell, an I/O block, and an
expander product term array.
Latch:
A level-sensitive clocked memory device (cell) that stores a single bit of data.
A High to low transition on the Latch Enable signal fixes the contents of the latch at
the value of the data input until the next Low-to-High transition on Latch Enable.
