Digital Signal Processing Reference
In-Depth Information
Memory is initialized only at the start of the simulation. A reset does not re-
initialize memory.
The execution of a short test program can be seen in the MIPS simulation
output shown in Figure 14.10. The program loads two registers from memory
with the LW instructions, adds the registers with an ADD, and stores the sum
with SW. Next, the program does not take a BEQ conditional branch with a
false branch condition. Last, the program loops back to the start of the program
at PC = 000 with another BEQ conditional branch with a true branch condition.
Figure 14.10
Simulation of MIPS test program.
14.10 MIPS Hardware Implementation on the FPGA Board
A special version of the top level of the MIPS, VIDEO_MIPS.VHD, is identical
to MIPS.VHD except that it also contains a VGA video output display driver.
As seen in Figure 14.11, this driver displays the hexadecimal value of major
busses in the MIPS processor on a monitor. The video character generation
technique used is discussed in Chapter 10. On the FPGA boards, it also displays
the PC in the LCD or LED displays. All FPGA boards use pushbuttons for the
clock and reset inputs. The clock pushbutton toggles the processor clock so you
can see the data changes occurring on each clock edge as you step through
MIPS machine instructions. This top-level module should be used instead of
MIPS.VHD after the design has been debugged in simulations. The final design
with video output is then downloaded to the FPGA chip on the board. The
video driver uses two M4K RAM embedded memory blocks for format and
character font data.
