Digital Signal Processing Reference
In-Depth Information
After simulation with MIPS.VHD, recompile using VIDEO_MIPS.VHD and
download the design to the FPGA board for hardware verification. Attach a
VGA monitor to the board's VGA connector. Any changes or additions made to
top level signal names in MIPS.VHD and other modules as suggested in the
exercises will need to also be cut and pasted into VIDEO_MIPS.VHD.
Figure 14.11
MIPS with Video Output generated by UP3 Board.
14.11 For Additional Information
The MIPS processor design and pipelining are described in the widely-used
Patterson and Hennessy textbook,
Computer Organization and Design The
Hardware/Software Interface
, Third Edition, Morgan Kaufman Publishers,
2005. The MIPS instructions are described in Chapter 2 and Appendix A of this
text. The hardware design of the MIPS, used as the basis for this model, is
described in Chapters 5 and 6 of the Patterson and Hennessy text.
SPIM, a free MIPS R2000 assembly language assembler and PC-based
simulator developed by James Larus, is available free from
http://www.cs.wisc.edu/~larus/spim.html
. The reference manual for the SPIM
simulator contains additional explanations of all of the MIPS instructions.
The MIPS instruction set and assembly language programming is also
described in J. Waldron,
Introduction to RISC Assembly Language
Programming
, Addison Wesley, 1999, and Kane and Heinrich,
MIPS RISC
Architecture
, Prentice Hall, 1992.
A
SMALLER VERSION OF THE
MIPS
PROCESSOR FOR THE
UP1
AND
UP2
IS
P
ROVIDED ON THE
DVD.
8-
BIT DATA IS USED WITH ONLY
8
REGISTERS
.
