Digital Signal Processing Reference
In-Depth Information
data_memory: altsyncram
GENERIC
MAP
(
operation_mode => "SINGLE_PORT",
width_a => 32,
widthad_a => 8,
lpm_type => "altsyncram",
outdata_reg_a => "UNREGISTERED",
-- Reads in mif file for initial data memory values
init_file => "dmemory.mif",
intended_device_family => "Cyclone"lpm_widthad
=>
8
)
PORT
MAP
(
wren_a => memwrite,
clock0 => write_clock,
address_a => address,
data_a => write_data,
q_a => read_data );
-- Load memory address & data register with write clock
write_clock <=
NOT
clock;
END
behavior;
MIPS data memory is initialized to the value specified in the file dmemory.mif
shown in Figure 14.9. Note that the address displayed in the dmemory.mif file
is a word address and not a byte address. Two values, 0x55555555 and
0xAAAAAAA, at byte address 0 and 4 are used for memory data in the short
test program. The remaining locations are all initialized to zero.
-- MIPS Data Memory Initialization File
Depth
= 256;
Width
= 32;
Content
Begin
-- default value for memory
[00..FF] : 00000000;
-- initial values for test program
00 : 55555555;
01 : AAAAAAAA;
End
;
Figure 14.9
MIPS Data Memory Initialization File, dmemory.mif.
14.9 Simulation of the MIPS Design
The top-level file MIPS.VHD is compiled and used for simulation of the MIPS.
It uses VHDL component instantiations to connect the five submodules. The
values of major busses and important control signals are output at the top level
for use in simulations. A reset is required to start the simulation with PC = 0. A
clock with a period of approximately 200ns is required for the simulation.
