A RISC Design: Synthesis of the MIPS Processor Core - Rapid Prototyping of Digital Systems - page 300

14.8 The Data Memory Stage
The data memory stage of the MIPS core shown in Figure 14.8 contains the
data memory. To speed synthesis and simulation, data memory is limited to 256
locations of 32-bit memory. Data memory is implemented using the Altsyncram
megafunction. Memory write cycle timing is critical in any design. The
Altsyncram function requires an internal address register with a clock. In this
design, the falling clock edge is used to load the data memories internal address
register. The rising clock edge starts the next instruction. Two M4K RAM
blocks are used for data memory. Two M4K RAM blocks are also used for the
32-bit instruction memory.

MemWrite

Data
Memory

Address

Read
Data

Write
Data

MemRead

Figure 14.8 Block Diagram of MIPS Data Memory Unit.

-- Dmemory module (implements the data
-- memory for the MIPS computer)

LIBRARY IEEE ;
USE IEEE . STD_LOGIC_1164 . ALL ;
USE IEEE .STD_LOGIC_ARITH. ALL ;
USE IEEE .STD_LOGIC_SIGNED. ALL ;
LIBRARY altera_mf;
USE altera_mf.atlera_mf_components. ALL ;

ENTITY dmemory IS

PORT ( read_data : OUT STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

address : IN STD_LOGIC_VECTOR ( 7 DOWNTO 0 );

write_data : IN STD_LOGIC_VECTOR ( 31 DOWNTO 0 );

MemRead, Memwrite : IN STD_LOGIC ;

clock, reset : IN STD_LOGIC );

END dmemory;

ARCHITECTURE behavior OF dmemory IS
SIGNAL write_clock : STD_LOGIC ;
BEGIN