Digital Signal Processing Reference
In-Depth Information
0
M
x
ADD
ADD
Result
PC + 4
1
ADD
Shift
Left
2
4
RegDst
Branch
MemRead
MemtoReg
ALUOp
MemWrite
ALUSrc
RegW
rite
Instruction
[3126]
Control
Unit
Instruction
Memory
Registers
Instruction
[2521]
Instruction
[2016]
Read
Register 1
Read
Register 2
Read
Address
Read
Data 1
PC
Instruction
[310]
Zero
Data
Memory
0
Instruction
[1511]
ALU
u
x
Write
Register
Address
ALU
Result
Read
Data 2
1
Read
Data
1
M
x
0
x
Write
Data
0
1
Write
Data
Instruction
[150]
16
32
Sign
Extend
ALU
Control
Instruction
[50]
Figure 14.1
MIPS Single Clock Cycle Implementation.
The two outputs of the register file then feed into the data ALU inputs. The
control units setup the ALU operation required to execute the instruction. Next,
Load and Store instructions read or write to data memory. R-format instructions
bypass data memory using a multiplexer. Last, R-format and Load instructions
write back a new value into the register file.
PC-relative branch instructions use the adder and multiplexer shown above the
data ALU in Figure 14.1 to compute the branch address. The multiplexer is
required for conditional branch operations. After all outputs have stabilized, the
next clock loads in the new value of the PC and the process repeats for the next
instruction.
RISC instruction sets are easier to pipeline. With pipelining, the fetch, decode,
execute, data memory, and register file write operations all work in parallel. In
a single clock cycle, five different instructions are present in the pipeline. The
basis for a pipelined hardware implementation of the MIPS is shown in Figure
14.2.
Additional complications arise because of data dependencies between
instructions in the pipeline and branch operations. These problems can be
resolved using hazard detection, data forwarding techniques, and branch
