A RISC Design: Synthesis of the MIPS Processor Core - Rapid Prototyping of Digital Systems - page 285

Table 14.2 MIPS Processor Core Instructions.

Mnemonic Format Opcode
Field

Function
Field

Instruction

Add R 0 32 Add

Addi I 8 Add Immediate

Addu R 0 33 Add Unsigned

Sub R 0 34 Subtract

Subu R 0 35 Subtract Unsigned

And R 0 36 Bitwise And

Or R 0 37 Bitwise OR

Sll R 0 0 Shift Left Logical

Srl R 0 2 Shift Right Logical

Slt R 0 42 Set if Less Than

Lui I 15 Load Upper Immediate

Lw I 35 Load Word

Sw I 43 Store Word

Beq I 4 Branch on Equal

Bne I 5 Branch on Not Equal

J J 2 Jump

Jal J 3 Jump and Link (used for Call)

Jump Register (used for
Return)

Jr R 0 8

A summary of the basic MIPS instructions is shown in Table 14.2. In depth
explanations of all MIPS instructions and assembly language programming
examples can be found in the references listed in section 14.11.
A hardware implementation of the MIPS processor core based on the example
in the widely used textbook, Computer Organization and Design The
Hardware/Software Interface by Patterson and Hennessy, is shown in Figure
14.1. This implementation of the MIPS performs fetch, decode, and execute in
one clock cycle. Starting at the left in Figure 14.1, the program counter (PC) is
used to fetch the next address in instruction memory. Since memory is byte
addressable, four is added to address the next 32-bit (or 4-byte) word in
memory. At the same time as the instruction fetch, the adder above instruction
memory is used to add four to the PC to generate the next address. The output
of instruction memory is the next 32-bit instruction.
The instruction's opcode is then sent to the control unit and the function code is
sent to the ALU control unit. The instruction's register address fields are used
to address the two-port register file. The two-port register file can perform two
independent reads and one write in one clock cycle. This implements the
decode operation.