Digital Signal Processing Reference
In-Depth Information
14 A RISC Design: Synthesis of the MIPS Processor Core
14.1 The MIPS Instruction Set and Processor
The MIPS is an example of a modern reduced instruction set computer (RISC)
developed in the 1980s. The MIPS instruction set is used by NEC, Nintendo,
Motorola, Sony, and licensed for use by numerous other semiconductor
manufacturers. It has fixed-length 32-bit instructions and thirty-two 32-bit
general-purpose registers. Register 0 always contains the value 0. A memory
word is 32 bits wide.
As seen in Table 14.1, the MIPS has only three instruction formats. Only I-
format LOAD and STORE instructions reference memory operands. R-format
instructions such as ADD, AND, and OR perform operations only on data in the
registers. They require two register operands, Rs and Rt. The result of the
operation is stored in a third register, Rd. R-format shift and function fields are
used as an extended opcode field. J-format instructions include the jump
instructions.
Table 14.1 MIPS 32bit Instruction Formats.
Field Size
6-bits
5-bits
5-bits
5-bits
5-bits
6-bits
R - Format
Opcode
Rs
Rt
Rd
Shift
Function
I - Format
Opcode
Rs
Rt
Address/immediate value
J - Format
Opcode
Branch target address
LW is the mnemonic for the Load Word instruction and SW is the mnemonic
for Store Word. The following MIPS assembly language program computes
A = B + C.
LW $2, B
;Register 2 = value of memory at address B
LW $3, C
;Register 3 = value of memory at address C
ADD $4, $2, $3
;Register 4 = B + C
SW $4, A
;Value of memory at address A = Register 4
The MIPS I-format instruction, BEQ, branches if two registers have the same
value. As an example, the instruction BEQ $1, $2, LABEL jumps to LABEL if
register 1 equals register 2. A branch instruction's address field contains the
offset from the current address. The PC must be added to the address field to
compute the branch address. This is called PC-relative addressing.
LW and SW instructions contain an offset and a base register that are used for
array addressing. As an example, LW $1, 100($2) adds an offset of 100 to the
contents of register 2 and uses the sum as the memory address to read data
from. The value from memory is then loaded into register 1. Using register 0,
which always contains a 0, as the base register disables this addressing feature.
