Digital Signal Processing Reference
In-Depth Information
flushing. With pipelining, most RISC instructions execute in one clock cycle.
Branch instructions will still require flushing of the pipeline. Exercises that add
pipelining to the processor core are included at the end of the chapter.
PCSrc
0
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ID/EX
WB
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Registers
Shift
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Read
Register 1
Read
Register 2
B
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nch
ALUSrc
Instruction
Memory
Read
Data 1
Zero
Write
Register
ALU
Data
Memory
PC
Address
Read
Data 2
ALU
Result
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Address
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Data
x
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Write
Data
Instruction
[150]
16
32
6
Sign
Extend
ALU
Control
Instruction
[2016]
Instruction
[1511]
MemRead
ALUOp
0
u
x
1
RegDst
Figure 14.2
MIPS Pipelined Implementation.
14.2 Using VHDL to Synthesize the MIPS Processor Core
A VHDL-synthesis model of the MIPS single clock cycle model from Figure
14.1 will be developed in this section. This model can be used for simulation
and implemented using the UP3 board.
The full 32-bit model requires a couple minutes to synthesize. When testing
new changes you might want to use the faster functional (i.e. no timing delays)
simulation approach before using a full timing delay model. This approach is
commonly used on larger models with long synthesis and simulation times.
A two-level hierarchy is used in the model. MIPS.VHD is the top-level of the
hierarchy. It consists of a structural VHDL model that connects the five
behavioral modules. The five behavioral modules are already setup so that they
correspond to the different stages for the MIPS. This makes it much easier to
modify when the model is pipelined in later laboratory exercises. For many
synthesis tools, hierarchy is also required to synthesize large logic designs.
IFETCH.VHD is the VHDL submodule that contains instruction memory and
the program counter. CONTROL.VHD contains the logic for the control unit.
