A Simple Computer Design: The uP 3 - Rapid Prototyping of Digital Systems - page 180

memory for instructions and data. The memory initialization file, program.mif
can be edited to change the loaded program. A write is performed only when
the memory_write signal is High. On a Cyclone FPGA device, the access time
for memory operations is in the range of 5-10ns.

-- Simple Computer Model Scomp.vhd

LIBRARY IEEE;
USE IEEE . STD_LOGIC_1164 . ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components. ALL ;

ENTITY SCOMP IS
PORT ( clock, reset : IN STD_LOGIC ;

program_counter_out : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 );

register_AC_out : OUT STD_LOGIC_VECTOR (15 DOWNTO 0 );

memory_data_register_out : OUT STD_LOGIC_VECTOR (15 DOWNTO 0 ));

memory_address_register_out : OUT STD_LOGIC_VECTOR (7 DOWNTO 0 );

memory_write_out : OUT STD_LOGIC );

END SCOMP;

ARCHITECTURE a OF scomp IS
TYPE STATE_TYPE IS ( reset_pc, fetch, decode, execute_add, execute_load, execute_store,
execute_store2, execute_jump );
SIGNAL state: STATE_TYPE;
SIGNAL instruction_register, memory_data_register : STD_LOGIC_VECTOR (15 DOWNTO 0 );

SIGNAL register_AC : STD_LOGIC_VECTOR (15 DOWNTO 0 );

SIGNAL program_counter : STD_LOGIC_VECTOR ( 7 DOWNTO 0 );

SIGNAL memory_address_register : STD_LOGIC_VECTOR ( 7 DOWNTO 0 );

SIGNAL memory_write : STD_LOGIC ;

BEGIN
-- Use Altsyncram function for computer's memory (256 16-bit words)
memory: altsyncram

GENERIC MAP (

operation_mode => "SINGLE_PORT",

width_a => 16,

widthad_a => 8,

lpm_type => "altsyncram",

outdata_reg_a => "UNREGISTERED",

-- Reads in mif file for initial program and data values

init_file => "program.mif",

intended_device_family => "Cyclone")

PORT MAP (wren_a => memory_write, clock0 => clock,
address_a =>memory_address_register, data_a => Register_AC,
q_a => memory_data_register );
-- Output major signals for simulation
program_counter_out <= program_counter;
register_AC_out <= register_AC;
memory_data_register_out <= memory_data_register;
memory_address_register_out <= memory_address_register;