Digital Signal Processing Reference
In-Depth Information
those in personal computers are both pipelined and superscalar. An example of
a pipelined, reduced instruction set computer (RISC) design can be found in
Chapter 14.
9.3 VHDL Model of the
Μ
P 3
To demonstrate the operation of a computer, a VHDL model of the ΜP 3
computer is shown in Figure 9.11. The simple ΜP 3 computer design fits easily
into a FPGA device using less than 1-10% of its logic. The computer's RAM
memory is implemented using the Altsyncram function which uses the FPGA's
internal memory blocks.
The remainder of the computer model is basically a VHDL-based state machine
that implements the fetch, decode, and execute cycle. The first few lines
declare internal registers for the processor along with the states needed for the
fetch, decode and execute cycle. A long CASE statement is used to implement
the control unit state machine. A reset state is needed to initialize the processor.
In the reset state, several of the registers are reset to zero and a memory read of
the first instruction is started. This forces the processor to start executing
instructions at location 00 in a predictable state after a reset.
The fetch state adds one to the PC and loads the instruction into the instruction
register (IR). After the rising edge of the clock signal, the decode state starts. In
decode, the low eight bits of the instruction register are used to start a memory
read operation in case the instruction needs a data operand from memory. The
decode state contains another CASE statement to decode the instruction using
the opcode value in the high eight bits of the instruction. This means that the
computer can have up to 256 different instructions, although only four are
implemented in the basic model. Other instructions can be added as exercises.
After the rising edge of the clock signal, control transfers to an execute state
that is specific for each instruction.
Some instructions can execute in one clock cycle and some instructions may
take more than one clock cycle. Instructions that write to memory will require
more than one state for execute because of memory timing constraints. As seen
in the STORE instruction, the memory address and data needs to be stable
before and after the memory write signal is High, hence, additional states are
used to avoid violating memory setup and hold times. When each instruction
finishes the execute state, MAR is loaded with the PC to start the fetch of the
next instruction. After the final execute state for each instruction, control
returns to the fetch state.
Since the FPGA's synchronous memory block requires and contains an internal
memory address and memory write register, it is necessary to make all
assignments to the memory address register and memory write outside of the
process to avoid having two cascaded registers. Recall that any assignment
made in a clocked process synthesizes registers. Two cascaded MAR registers
would require a delay of two clocks to load a new address for a memory
operation.
The machine language program shown in Figure 9.12 is loaded into memory
using a memory initialization file (*.mif). This produces 256 words of 16-bit
