Digital Signal Processing Reference
In-Depth Information
states examined, a maximum of three buses were used for register transfers.
Timing in critical paths, such as ALU delays and memory access times, will
determine the clock speed at which these operations can be performed.
IR
00 12
00 03
00 04
ALU
00 07
register_AC
00 04
PC
02
16
8
16
02
MAR
12
Memory
00:
02 11
01:
00 12
02:
01 10
03:
03 03
10:
00 00
11:
00 04
12: 00 03
MDR
00 03
Figure 9.10
Register transfers in the ADD instruction's Execute State.
The ΜP 3's
multiple clock cycles per instruction implementation approach was
used in early generation microprocessors. These computers had limited
hardware, since the VLSI technology at that time supported orders of
magnitude fewer gates on a chip than is now possible in current devices.
Current generation processors, such as those used in personal computers, have
a hundred or more instructions, and use additional means to speedup program
execution. Instruction formats are more complex with up to 32 data registers
and with additional instruction bits that are used for longer address fields and
more powerful addressing modes.
Pipelining converts fetch, decode, and execute into a parallel operation mode
instead of sequential. As an example, with three stage pipelining, the fetch unit
fetches instruction n + 2, while the decode unit decodes instruction n + 1, and
the execute unit executes instruction n. With this faster pipelined approach, an
instruction finishes execution every clock cycle rather than three as in the
simple computer design presented here.
Superscalar machines are pipelined computers that contain multiple fetch,
decode and execute units. Superscalar computers can execute several
instructions in one clock cycle. Most current generation processors including
