Using Verilog for Synthesis of Digital Hardware - Rapid Prototyping of Digital Systems - page 141

Verilog Memory Model - Example One
The first memory example synthesizes a memory that can perform a read and a
write operation every clock cycle. Memory is built using arrays of positive
edge-triggered D flip-flops. Memory write, memwrite, is gated with an address
decoder output and used as an enable to load each memory location during a
write operation. A synchronous write operation is more reliable. Asynchronous
write operations respond to any logic hazards or momentary level changes on
the write signal. As in any synchronous memory, the write address must be
stable before the rising edge of the clock signal. A non-clocked mux is used for
the read operation. If desired, memory can be initialized by a reset signal.
module memory ( read_data, read_address, write_data, write_address,
memwrite, clock, reset );
output [7:0] read_data ;
input [2:0] read_address ;
input [7:0] write_data ;
input [2:0] write_address ;
input memwrite ;
input clock ;
input reset ;
reg [7:0] read_data, mem0, mem1 ;
/* Block for memory read */
always @( read_address or mem0 or mem1 )
begin
case( read_address )
3'b 000: read_data = mem0 ;
3'b 001: read_data = mem1 ;
/* Unimplemented memory */
default: read_data = 8'h FF;
endcase
end
/* Block for memory write */
always @(posedge clock or posedge reset )
begin
if ( reset )
begin
/* Initial values for memory (optional) */
mem0 = 8'h AA ;
mem1 = 8'h 55;
end
else if ( memwrite )
/* write new value to memory */
case ( write_address )
3'b 000 : mem0 = write_data ;
3'b 001 : mem1 = write_data ;
endcase
end
endmodule