Using Verilog for Synthesis of Digital Hardware - Rapid Prototyping of Digital Systems - page 140

module mult ( dataa, datab, result );
input [7:0] dataa ;
input [7:0] datab ;
output [15:0] result ;
wire [15:0] sub_wire0 ;
wire [15:0] result = sub_wire0 [15:0];
/* Altera LPM 8x8 multiply function result = dataa * datab */
lpm_mult lpm_mult_component (
.dataa ( dataa ),
.datab ( datab ),
.result ( sub_wire0 ) );
defparam
lpm_mult_component.lpm_widtha = 8,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 16,
lpm_mult_component.lpm_widths = 1,
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_representation = "UNSIGNED",
endmodule
Floating-point operations can be implemented on very large FPGAs; however,
performance is lower than current floating-point DSP and microprocessor
chips. The floating-point algorithms must be coded by the user in Verilog using
integer add, multiply, divide, and shift operations. The LPM_CLSHIFT
function is useful for the barrel shifter needed in a floating-point ALU. Some
floating point IP cores are starting to appear. Many FPGA vendors also have
optimized arithmetic packages for DSP applications such as FIR filters.
7.14 Verilog Synthesis Models for Memory
Typically, it is more efficient to call a vendor-specific function to synthesize
RAM. These functions typically use the FPGA's internal RAM blocks rather
than building a RAM using FPGA logic elements. The memory function in the
Altera toolset is the ALTSYNCRAM function. On the UP2 board's older
FPGA, the LPM_RAM_DQ memory function should be used. The memory can
be set to an initial value using a separate memory initialization file with the
extension *.mif. A similar call, LPM_ROM, can be used to synthesize ROM.
If small blocks of multi-ported or other special-purpose RAM are needed, they
can be synthesized using registers with address decoders for the write operation
and multiplexers for the read operation. Additional read or write ports can be
added to synthesize RAM. An example of this approach is a dual-ported
register file for a computer processor core. Most RISC processors need to read
two registers on each clock cycle and write to a third register.