Digital Signal Processing Reference
In-Depth Information
inputs and the "+" operator would be used only in a single assignment
statement.
module
ALU
(
ALU_control, Ainput, Binput, Clock, Shift_output
);
input [2:0]
ALU_control
;
input [15:0]
Ainput
;
Ainp ut
Bin put
input [15:0]
Binput
;
input
Clock
;
16
16
output[15:0]
Shift_output
;
reg [15:0]
Shift_output
;
A L U
+, , AND, OR
reg [15:0]
ALU_output
;
ALU_ cont r ol ( 2 .. 1)
/* Select ALU Arithmetic/Logical Operation */
always @(
ALU_control
or
Ainput
or
Binput
)
AL U_o ut put
16
case (
ALU_control
[2:1])
0:
ALU_output
=
Ainput
+
Binput
;
ALU _con tro l(0)
Shi ft Lef t
1:
ALU_output
=
Ainput
-
Binput
;
16
2:
ALU_output
=
Ainput
&
Binput
;
Cl ock
3:
ALU_output
=
Ainput
|
Binput
;
Reg ist er
default:
ALU_output
= 0;
16
endcase
Shif t_ out put
/* Shift bits left using shift left operator if required and load register */
always @(posedge
Clock
)
if (
ALU_control
[0]==1)
Shift_output
=
ALU_output
<<
1
;
else
Shift_output
=
ALU_output
;
endmodule
7.13 Verilog Synthesis of Multiply and Divide Hardware
In the Quartus II tool, integer multiply and divide is supported using Verilog's
"*" and "/" operators. In current generation tools, efficient design of multiply or
divide hardware typically requires the use of a vendor-specific library function
or even the specification of the arithmetic algorithm and hardware
implementation in Verilog.
A wide variety of multiply and divide algorithms that trade off time versus
hardware size can be found in most computer arithmetic texts. Several such
references are listed at the end of this chapter. These algorithms require a
sequence of add/subtract and shift operations that can be easily synthesized in
Verilog using the standard operators. The LPM_MULT function in Quartus II
can be used to synthesize integer multipliers. LPM_DIVIDE, is also available.
When using LPM functions,
To o l s MegaWizard
Plug-in Manager
can be
used to help generate Verilog code. The LPM functions also support pipeline
options. Array multiply and divide hardware for more than a few bits requires
extensive hardware and a large FPGA. A few large FPGAs now contain
multiplier blocks.
