Digital Signal Processing Reference
In-Depth Information
/* Make State Assignments */
parameter [1:0]
state_A
= 0,
state_B
= 1,
state_C
= 2;
always@(posedge
clk
or posedge
reset
)
begin
if (
reset
)
state
=
state_A
;
else
/* Define Next State Transitions using a Case */
/* Statement based on the Current State */
case (
state
)
state_A
:
if (
input1
==0)
state
=
state_B
;
else
state
=
state_C
;
state_B
:
state
=
state_C
;
state_C
:
if
(input2
)
state
=
state_A
;
f l t :
state
=
state_A
;
endcase
end
/* Define State Machine Outputs */
always @(
state
)
begin
case (
state
)
state_A
:
output1
= 0;
state_B
:
output1
= 1;
state_C
:
output1
= 0;
default:
output1
= 0;
endcase
end
endmodule
7.12 Verilog Synthesis Model of an ALU with an
Adder/Subtractor and a Shifter
Here is an 8-bit arithmetic logic unit (ALU) that adds, subtracts, bitwise ANDs,
or bitwise ORs, two operands and then performs an optional shift on the output.
The most-significant two bits of the Op-code select the arithmetic logical
operation. If the least-significant bit of the op_code equals '1' a 1-bit left-shift
operation is performed. An addition and subtraction circuit is synthesized for
the "+" and "-" operator.
Depending on the number of bits and the speed versus area settings in the
synthesis tool, ripple carry or carry-lookahead circuits will be used. Several "+"
and "-" operations in multiple assignment statements may generate multiple
ALUs and increase the hardware size, depending on the Verilog CAD tool and
compiler settings used. If a single ALU is desired, muxes can be placed at the
