Using Verilog for Synthesis of Digital Hardware - Rapid Prototyping of Digital Systems - page 137

module counter ( clock, reset, max_count, count );

input clock ;

input reset ;

input [7:0] max_count ;

output [7:0] count ;

reg [7:0] count ;

/* use positive clock edge for counter */

always @(posedge clock or posedge reset )

begin

if ( reset )

count = 0; /* Reset Counter */

else if ( count < max_count ) /* Check for maximum count */

count = count + 1; /* Increment Counter */

else

count = 0; /* Counter set back to 0*/

end

endmodule

7.11 Verilog Synthesis Model of a State Machine
The next example shows a Moore state machine with three states, two inputs
and a single output. A state diagram of the example state machine is shown in
Figure 7.1. Unlike VHDL, A direct assignment of the state values is required in
Verilog's parameter statement. The first Always block assigns the next state
using a case statement that is updated on the positive clock edge, posedge.

Re s et

A

0X

1X

X1

B
Output1

C

X0

Figure 7.1 State Diagram for state_mach Verilog example

module state_mach ( clk, reset, input1, input2 ,output1 );

input clk, reset, input1, input2 ;

output output1 ;

reg output1 ;

reg [1:0] state ;