Digital Signal Processing Reference
In-Depth Information
device may not support every flip-flop or latch type and all of the Set/Reset and
Enable options.
If D and Q are replaced by bit vectors in any of these examples, registers with
the correct number of bits will be generated instead of individual flip-flops.
7.9 Accidental Synthesis of Inferred Latches
Here is a very common problem to be aware of when coding Verilog for
synthesis. If a non-clocked process has any path that does not assign a value to
an output, Verilog assumes you want to use the previous value. A level
triggered latch is automatically generated or inferred by the synthesis tool to
save the previous value. In many cases, this can cause serious errors in the
design. Edge-triggered flip-flops should not be mixed with level-triggered
latches in a design or serious timing problems will result. Typically this can
happen in CASE statements or nested IF statements. In the following example,
the signal Output2 infers a latch when synthesized. Assigning a value to
Output2 in the last ELSE clause will eliminate the inferred latch. Warning
messages may be generated during compilation when a latch is inferred on
some tools. Note the use of
begin…end
is somewhat different than the use of
braces in C.
module
ilatch
(
A, B, Output1, Output2
);
input
A, B
;
output
Output1, Output2
;
reg
Output1, Output2
;
always@(
A
or
B
)
if (!
A
)
begin
Output1
= 0;
D Q
Output2
= 0;
Output2
end
else
if (
B
)
Clock
begin
Output1
= 1;
Output2
= 1;
end
else
/*latch inferred since no value */
Output1
= 0;
/*is assigned to Output2 here */
endmodule
7.10 Verilog Synthesis Model of a Counter
Here is an 8-bit counter design. Compare operations such as “<” are supported
and they generate a comparator logic circuit to test for the maximum count
value. The assignment count = count+1; synthesizes an 8-bit incrementer. An
incrementer circuit requires less hardware than an adder that adds one. The
operation, "+1", is treated as a special incrementer case by synthesis tools.
