Digital Signal Processing Reference
In-Depth Information
7.8 Verilog Synthesis Models of Flip-flops and Registers
In the next example, several flip-flops will be generated. Unlike earlier
combinational hardware devices, a flip-flop can only be synthesized inside an
always statement. The positive clock edge is selected by
posedge clock
and
positive edge triggered D flip-flops will be used for synthesis. The following
module contains a variety of Reset and Enable options on positive edge-
triggered D flip-flops. The negative clock edge is selected by
negedge clock
and negative edge-triggered D flip-flops used during synthesis.
module
DFFs
(
D, clock, reset, enable, Q1, Q2, Q3, Q4
);
D
D Q
Q1
input
D
;
input
clock
;
input
reset
;
Clock
input
enable
;
output
Q1, Q2, Q3, Q4
;
reg
Q1, Q2, Q3, Q4
;
/* Positive edge triggered D flip-flop */
always @(posedge
clock
)
Reset
Q1
=
D
;
D
0
0
D Q
Q2
/* Positive edge triggered D flip-flop */
1
/* with synchronous reset */
always @(posedge
clock
)
if (
reset
)
Clock
Q2
=
0
;
else
Q2
=
D
;
/* Positive edge triggered D flip-flop */
Reset
/* with asynchronous reset */
always @(posedge
clock
or posedge
reset
)
D
D Q
Q3
if (
reset
)
Q3
= 0;
else
Clock
Q3
=
D
;
/* Positive edge triggered D flip-flop */
/* with asynchronous reset and enable */
always @(posedge
clock
or posedge
reset
)
Reset
if (
reset
)
Enable
Q4
= 0;
Q4
0
1
else if (
enable
)
D Q
Q4
D
Q4
=
D
;
endmodule
Clock
In Verilog, as in any digital logic designs, it is not good design practice to AND
or gate other signals with the clock. Use a flip-flop with a clock enable instead
to avoid timing and clock skew problems. In some limited cases, such as power
management, a single level of clock gating can be used. This works only when
a small amount of clock skew can be tolerated and the signal gated with the
clock is known to be hazard or glitch free. A particular programmable logic
