Digital Signal Processing Reference
In-Depth Information
statement can be used for a 2-to-1 mux. A concurrent assign statement can also
be used instead of wire, if the output signal is already declared. In Verilog, IF
and CASE statements must be inside an always statement. The inputs and
outputs from the multiplexers could be changed to bit vectors if an entire bus is
multiplexed. Multiplexers with more than two inputs can also be easily
constructed and a case statement is preferred. Nested IF statements generate
priority-encoded logic that requires more hardware and produce a slower circuit
than a CASE statement.
/* Multiplexer example shows three ways to model a 2 to 1 mux */
module
multiplexer
(
A, B, mux_control, mux_out1, mux_out2, mux_out3
);
input
A
;
/* Input Signals and Mux Control */
input
B
;
input
mux_control
;
output
mux_out1,mux_out2, mux_out3
;
reg
mux_out2, mux_out3
;
/* Conditional Continuous Assignment Statement */
/* works like an IF - ELSE */
wire
mux_out1
= (
mux_control
)?
B
:
A
;
/* If statement inside always statement */
always @(
A
or
B
or
mux_control
)
Mux_Control
if (
mux_control
)
A
0
mux_out2
=
B
;
Mux_Out
x
else
mux_out2
=
A
;
/* Case statement inside always statement */
always @(
A
or
B
or
mux_control
)
B
1
case (
mux_control
)
0:
mux_out3
=
A
;
1:
mux_out3
=
B
;
default
: mux_out3
=
A
;
endcase
endmodule
7.7 Verilog Synthesis Model of Tri-State Output
Tri-state gates are supported in Verilog synthesis tools and are supported in
many programmable logic devices. Most programmable logic devices have tri-
state output pins. Some programmable logic devices do not support internal tri-
state logic. Here is a Verilog example of a tri-state output. In Verilog, the
assignment of the value "Z" to a signal produces a tri-state output.
module
tristate
(
a, control, tri_out
);
input
a, control
;
output
tri_out
;
reg
tri_out
;
always @(
control
or
a
)
Control
if (
control
)
/* Assignment of Z value generates a tri-state output */
tri_out
=
1'bZ;
A
Tri_Out
else
tri_out
=
a
;
endmodule
