Digital Signal Processing Reference
In-Depth Information
6.7 VHDL Synthesis Model of Tri-State Output
Tri-state gates are supported in VHDL synthesis tools and are supported in
many programmable logic devices. Most programmable logic devices have tri-
state output pins. Some programmable logic devices do not support internal tri-
state logic. Here is a VHDL example of a tri-state output. In VHDL, the
assignment of the value "Z" to a signal produces a tri-state output.
LIBRARY
IEEE
;
USE
IEEE
.
STD_LOGIC_1164
.
ALL
;
Control
A
Tri_Out
ENTITY
tristate
IS
PORT
( A, Control
:
IN
STD_LOGIC
;
Tri_out
:
INOUT
STD_LOGIC
);
-- Use Inout for bi-directional tri-state
-- signals or out for output only
END
tristate;
ARCHITECTURE
behavior
OF
tristate
IS
-- defines internal module architecture
BEGIN
Tri_out <= A
WHEN
Control = '0'
ELSE
'Z';
-- Assignment of 'Z' value generates
END
behavior;
-- tri-state output
6.8 VHDL Synthesis Models of Flip-flops and Registers
In the next example, several flip-flops will be generated. Unlike earlier
combinational hardware devices, a flip-flop can only be synthesized inside a
process. In VHDL, Clock'EVENT is true whenever the clock signal changes.
The positive clock edge is selected by (clock'EVENT AND clock = '1') and
positive edge triggered D flip-flops will be used for synthesis.
The following module contains a variety of Reset and Enable options on
positive edge-triggered D flip-flops. Processes with a wait statement do not
need a process sensitivity list. A process can only have one clock or reset type.
The negative clock edge is selected by (clock'EVENT AND clock = '0') and
negative edge-triggered D flip-flops will be generated during synthesis. If
(Clock = '1') is substituted for (clock'EVENT AND clock = '1') level-
triggered latches will be selected for logic synthesis. Rising_edge(clock) can
also be used instead of clock'EVENT AND clock = '1'. Falling_edge(clock) is
also supported for negative clock edges.
LIBRARY
IEEE
;
USE
IEEE
.
STD_LOGIC_1164
.
ALL
;
ENTITY
DFFs
IS
PORT
( D, Clock, Reset, Enable
:
IN
STD_LOGIC
;
Q1, Q2, Q3, Q4
:
OUT STD_LOGIC
);
END
DFFs;
