Using VHDL for Synthesis of Digital Hardware - Rapid Prototyping of Digital Systems - page 111

MSD_f <= NOT MSD_7SEG( 1 );
MSD_g <= NOT MSD_7SEG( 0 );

6.6 VHDL Synthesis Model of a Multiplexer
The next example shows several alternative ways to synthesize a 2-to-1
multiplexer in VHDL. Four identical multiplexers that operate in parallel are
synthesized by this example. In VHDL, IF and CASE statements must be inside
a process. The inputs and outputs from the multiplexers could be changed to
standard logic vectors if an entire bus is multiplexed. Multiplexers with more
than two inputs can also be easily constructed. Nested IF-THEN-ELSE
statements generate priority-encoded logic that requires more hardware and
produce a slower circuit than a CASE statement.

LIBRARY IEEE ;
USE IEEE . STD_LOGIC_1164 . ALL ;

ENTITY multiplexer IS -- Input Signals and Mux Control

PORT ( A, B, Mux_Control : IN STD_LOGIC ;

Mux_Control

Mux_Out1, Mux_Out2,

Mux_Out3, Mux_Out4 : OUT STD_LOGIC );

A 0

END multiplexer;

Mux_Out x

B

1

ARCHITECTURE behavior OF multiplexer IS
B E G

I N -- selected signal assignment statement…

Mux_Out1 <= A WHEN Mux_Control = '0' ELSE B;

- - … w i t h S e l e c t S t a t e e n t

WITH Mux_control SELECT

Mux_Out2 <= A WHEN '0',

B WHEN '1',

A WHEN OTHERS ; -- OTHERS case required since STD_LOGIC

-- has values other than "0" or "1"

PROCESS ( A, B, Mux_Control)

B E G I N -- Statements inside a process

I F Mux_Control = '0' THEN execute sequentially.

Mux_Out3 <= A;

ELSE

Mux_out3 <= B;

END IF ;

CASE Mux_Control IS

WHEN '0' =>

Mux_Out4 <= A;

WHEN '1' =>

u x _ O u t 4 < = B ;

WHEN OTHERS =>

u x _ O u t 4 < = A ;

END CASE ;
END PROCESS ;
END behavior;