Digital Signal Processing Reference
In-Depth Information
ARCHITECTURE
behavior
OF
DFFs
IS
E
I N
PROCESS
-- Positive edge triggered D flip-flop
E
I N
-- If WAIT is used no sensitivity list is used
WAIT
UNTIL
( Clock
'EVENT
AND
Clock = '1' );
Q1 <= D;
D
D Q
Q1
END
PROCESS
;
Clock
PROCESS
-- Positive edge triggered D flip-flop
BEGIN
-- with synchronous reset
WAIT
UNTIL
( Clock
'EVENT
AND
Clock = '1' );
IF
reset = '1'
THEN
Q2 <= '0';
Reset
ELSE
D
0
0
1
Q2 <= D;
D Q
Q2
END
IF
;
END
PROCESS
;
Clock
PROCESS
(Reset,Clock)
-- Positive edge triggered D flip-flop
E
I N
--
with asynchronous reset
IF
reset = '1'
THEN
Reset
Q3 <= '0';
ELSIF
( clock
'EVENT
AND
clock = '1' )
THEN
D
D Q
Q3
Q3 <= D;
END
IF
;
END
PROCESS
;
Clock
PROCESS
(Reset,Clock)
-- Positive edge triggered D flip-flop
E
I N
--
with asynchronous reset and
-- enable
IF
reset = '1'
THEN
Q4 <= '0';
ELSIF
( clock
'EVENT
AND
clock = '1' )
THEN
IF
Enable = '1'
THEN
Q4 <= D;
END
IF
;
END
IF
;
END
PROCESS
;
END
behavior;
In VHDL, as in any digital logic designs, it is not good design practice to AND
or gate other signals with the clock. Use a flip-flop with a clock enable instead
to avoid timing and clock skew problems. In some limited cases, such as power
management, a single level of clock gating can be used. This works only when
a small amount of clock skew can be tolerated and the signal gated with the
clock is known to be hazard or glitch free. A particular programmable logic
Reset
Enable
Q4
0
1
D Q
Q4
D
Clock
