Models for Delay Faults - Models in Hardware Testing - page 78

CUT

SC1 SC2 SC3

D Q D Q D Q SOUT

SIN

SD
SE
CK

SD
SE
CK

SD
SE
CK

SE
CK

Fig. 3.8 A scan chain

IP
n

LP CP

CLK

SE

Scan in pattern I
Scan out response i-1

Scan in pattern i+1
Scan out response i

Fig. 3.9 Timing diagram for two pattern tests using LOC test application method

clock cycle is applied to capture the circuit response to the test. SE is changed to 1
and the captured response is scanned out and at the same time the next test is shifted
in. For two pattern tests, two methods of test application called skewed-load ( Savir
et al. 1993 ) also called launch off shift (LOS) and broadside ( Savir et al. 1994 ) also
called launch off capture (LOC) are used. Both methods can be regarded to have
three phases. In the first phase, called initialization cycle or initialization phase (IP),
the first vector V1 of a two pattern test <V1,V2> is scanned in with SE D 1.
The two methods differ in the next phase called the launch phase or launch cycle
(LP). In LOS method the second vector V2 is obtained by shifting once with SE
staying at 1. Thus V2 is restricted to be a single shift of V1. In LOC test method
V2 is obtained through the combinational logic of the circuit by setting SE D 0.
Thus in LOC also V2 is obtained as a function of V1. In the third phase, called the
capture cycle (CP), in LOS method SE is changed to 0 and the response to the test
applied is captured. In LOC method SE is maintained at 0 and the response to the
test is captured as for the LOS method. The timing waveforms for the two methods
are shown in Figs. 3.9 and 3.10 . From the waveforms for the LOS method it can be