Hardware Reference
In-Depth Information
Tabl e 3. 1
Sensitization conditions on off-path inputs
Non-robust
Robust
Strong
Weak
Functional
AND
NAND
OR
NOR
AND
NAND
OR
NOR
AND
NAND
OR
NOR
AND
NAND
OR
NOR
Transition
0 ! 1
X1
S0
X1
H0
X1
X0
X1
XX
1 ! 0
S1
X0
H1
X0
X1
X0
XX
X0
0 0
b
d
0 1
g
b
0 1
0 1
1 1
f
0 1
0 1
c
1 1
a
h
e
0 0
a
0 1
Fig. 3.7
but may have a hazard/glitch. It may be necessary to consider subsets of paths or
be tested together and not separately. In general, it is necessary to consider what are
Tests for sequential circuits can be applied using slow and fast clocks (
Malaiya
using slow and fast clocks the initialization pattern is obtained using a slow clock
followed by the second vector of a two pattern test. Response to the second vector is
captured using a fast clock whose period is the desired clock period during normal
operation. The captured error values in flip-flops are then propagated to primary
outputs again using a slow clock. It is assumed that when a slow clock is applied the
circuit operates as a fault-free circuit. When only the system clock is used for delay
faults one has to accommodate the fact that the effect of the delay fault may remain
for one or more cycles (
Pomeranz et al.
1992
;
Cheng
1993
).
3.1.4
Delay Fault Tests for Scan Designs
Scan is universally used in large industrial designs to facilitate test generation, debug
and failure diagnosis of synchronous sequential circuits. In Fig.
3.8
a scan design
called MUX-Scan is illustrated. Single pattern tests are applied by shifting/scanning
in the state part of the test with scan enable (SE) at logic 1. After loading the scan
chain the primary input values for the test are applied. SE is changed to 0 and one