Hardware Reference
In-Depth Information
S 0
a
b
f
S 0
h
1 0
X X
k
1 0
0 1
g
c
d
0 1
S 0
j
X 0
e
X 1
Fig. 3.4
Robust test for path c-g-h-k with rising transition
0 1
a
b
f
H 0
h
1 0
1 0
k
1 0
0 1
g
c
d
0 1
S 0
j
X 0
e
X 1
Fig. 3.5
Strong non-robust test for path c-g-h-k with rising transition
1 0
a
b
1 0
f
h
H 0
1 0
k
X 0
0 1
g
c
d
0 1
S 0
j
X 0
e
X 1
Fig. 3.6
Weak non-robust test for path c-g-h-k with rising transition
Generation of tests for path delay faults and fault simulation have been exten-
sively investigated (
Krstic et al.
1998
;
Pomeranz et al.
1998
;
Bushnell et al.
2000
;
Jha et al.
2003
). Typically one uses the necessary conditions on off-path inputs of
the gates on the path for sensitizing the path to determine additional necessary con-
ditions through implications followed by justifying all the necessary conditions.
Path sensitization conditions for different types of two pattern tests are shown in
the two pattern test and H0(H1) represent a signal that is a 0(1) in the steady state
