Models for Delay Faults - Models in Hardware Testing - page 75

pattern t1 should set the value on the faulty line to 0(1) and (ii) the second pattern
t2 must detect a stuck-at-1(0) fault on the faulty line. The first pattern t1 is called
the initialization pattern that initializes the faulty line to a 0(1) for STR(STF) TDF
fault. Thus one can modify test pattern generators and fault simulators for stuck-at
faults in a straight forward manner to obtain similar tools for TDFs. This is one of
the advantages of the TDF model.
Tests for gate delay faults require accounting for delay defect size. For example
if the defect size at a circuit lead r is less than the slack of r the fault may not be
detectable by any test. Slack of a circuit line is the difference between the period
of the functional clock and the maximum delay of all paths through r. This requires
accurate timing models for signal propagation and accommodation of the fact that
signal propagation delays can only be modeled as a range between minimum and
maximum delays ( Iyengar et al. 1990 ; Pramanick et al. 1997 ). Additionally prop-
agation delay of a gate input depends on the states of the other inputs to the gates
and coupling capacitances to other adjacent lines. Another issue that crops up is the
fact that more than one test may be needed to detect all defect sizes at some fault
site that may cause malfunction at the desired frequency of operation ( Pramanick
et al. 1997 ) . Methods to determine a threshold value of defect size above which the
fault is detected by a given test have been developed ( Iyengar et al. 1990 ; Pramanick
et al. 1997 ; Dumas et al. 1993 ) . However, such methods pessimistically estimate the
defect sizes covered ( Pramanick et al. 1997 ) due to the fact that a given test may
detect a range of defect sizes instead of only defects with sizes larger than a thresh-
old. For gate delay faults, as well as transition faults, activation of faults by hazards
or glitches also needs to be considered ( Pramanick et al. 1997 ; Brand et al. 1994 ;
Pomeranz et al. 2009 b).
Path delay fault model ( Smith 1985 ) is more comprehensive since it can accom-
modate spot defects and distributed defects. A path delay fault is associated with
each logical path and is said to be present if the delay of the logical path exceeds
the slack of the path. Tests to detect path delay faults are classified according to the
conditions satisfied by the side inputs of the gates in the path. The different types of
tests are discussed below.
In Fig. 3.4 a robust test for the logical path c-g-h-k with rising transition at its
input is shown. The path delay fault test is called a robust test if it detects the fault
independent of the delays in the rest of the circuit ( Smith 1985 ; Lin et al. 1987 ) .
In Fig. 3.4 we show the signal values for the two pattern test where S0 represents
a signal value that is a glitch free 0 during the application of the two patterns. For
the same fault, in Figs. 3.5 and 3.6 non-robust tests called strong non-robust and
weak non-robust tests are shown. The signal value H0 represents a signal value
that is a 0 in the steady state but may have a hazard or glitch during the transition
from the first pattern to the second pattern of the two pattern test. Non-robust tests
can be invalidated due to circuit delays that effect signals at the off-path inputs
( Konuk 2000 ; Pomeranz et al. 2008 a ). For some paths neither robust nor non-robust
tests may exist. However such paths may be functional paths and should be tested
using functional sensitization ( Cheng et al. 1996 ) .