Models for Delay Faults - Models in Hardware Testing - page 70

Chapter 3
Models for Delay Faults

Sudhakar M. Reddy

Abstract In this chapter fault models used to model the effects of defects causing
excessive circuit delays are discussed. Methods to generate tests to detect modeled
faults and design for test methods to improve fault coverage are reviewed. Current
work in detecting what are called small delay defects is discussed.

Keywords Delay faults Delay fault testing Small delay defects Design for test

3.1 Introduction

Delay faults model defects that affect performance of logic circuits in contrast
to other fault models such as line stuck-at faults that model defects that affect
the functionality of circuits. Delay faults were first considered by Breuer in 1974
( Breuer 1974 ) and have been extensively studied since early 1980s. Electronic gates
and interconnects introduce finite delays in signal propagation in digital integrated
circuits. Process variations and defects in manufacturing could cause delays in some
gates and interconnects to be larger or smaller than the delays used for the design.
Common defects in VLSI circuits are opens and unwanted shorts/bridges between
circuit nodes. Resistive opens and bridges cause signal propagation delays to in-
crease at the defect site. Opens and bridges are discussed in detail in Chapters 1
and 2 , respectively. Larger delays cause data set up time violations at the inputs to
the storage elements (latches and flip-flops) of the design causing the manufactured
circuits to fail to operate correctly at the desired frequency of operation. These are
the faults that are typically called delay faults in the literature and are the subject of
this chapter. Smaller than modeled delays cause data hold time violations at storage
element inputs and cause the circuit to malfunction at all frequencies of operation.
Models for data hold time violations and tests to detect them have been investigated
in ( Reddy et al. 2000 ) and more extensively investigated in the context of diagnosing

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Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa, USA
e-mail: [e-mail]

S.M. Reddy (