Hardware Reference
In-Depth Information
Renovell M, Huc P, Bertrand Y (1994b) CMOS bridging fault modelling. VLSI test symposium,
pp 392-397
Renovell M, Huc P, Bertrand Y (1995) The concept of resistance interval: a new parametric model
for realistic resistive bridging fault. VLSI test symposium, pp 184-189
Renovell M, Azaıs F, Bertrand Y (1999) Detection of defects using fault model oriented test se-
quences. J Electron Testing: Theory Appl 14:13-22
Rodrıguez-Monta nes R, Segura J, Champac V, Figueras J, Rubio A (1990) Bridging faults in
CMOS: possibilities of current testing. European solid-state circuit conference, pp 117-120
Rodrıguez-Monta nes R, Segura JA, Champac VH, Figueras J, Rubio JA (1991) Current vs. logic
testing of gate oxide shorts, floating gate and bridging failures in CMOS. International test
conference, pp 510-519
Rodrıguez-Monta nes R, Bruls EMJG, Figueras J (1992) Bridging defects resistance measurements
in CMOS process. International test conference, pp 892-899
Rodrıguez-Monta nes R, Bruls EMJG, Figueras J (1996) Bridging defects resistance in the metal
layer of a CMOS process. J Electron Testing: Theory Appl 8:35-46
Rodrıguez-Monta nes R, Arumı D, Figueras J (2006) Effectiveness of very low voltage testing of
bridging defects. IEE Electron Lett 42(19):1083-1084
Rubio A, Figueras J, Champac V, Rodrıguez R, Segura J (1991) I
DDQ
secondary components in
CMOS logic circuits preceded by defective stages affected by analogue type faults. IEE Elec-
tron Lett 27(18):1656-1658
Sachdev M (1997) Deep sub-micron I
DDQ
testing: issues and solutions. European design and test
conference, pp 271-278
Sar-Dessai VR, Walker DMH (1999) Resistive bridge fault modeling, simulation and test genera-
tion. International test conference, pp 596-605
Schuermyer C, RuMer J, Daasch R (2004) Minimum testing requirements to screen temperature
dependent defects. International test conference, pp 300-308
Semenov O, Sachdev M (2000) Impact of technology scaling on bridging fault detection in se-
quential and combinational CMOS circuits. International workshop on defect based testing,
pp 36-42
Soden JM, Hawkins CF (1996) I
DDQ
testing: issues present and future. IEEE Des Test Comput
13:61-65
Thibeault C (1997) A novel probabilistic approach for IC diagnosis based on differential quiescent
current signatures. VLSI test symposium, pp 80-85
Thibeault C, Boisvert L (1998) Diagnosis method based on Iddq probabilistic signatures: exper-
imental results. International test conference, pp 1019-1026
Thibeault C (Jun 2000) On the adaptation of Viterbi algorithm for diagnosis of multiple bridging
faults. IEEE Trans Comput 49:575-587
Turner ME, Leet DG, Prilik RJ, McLean DJ (1985) Testing CMOS VLSI: tools, concepts and
experimental results. International test conference, pp 322-328
Wu J, Rudnick EM (1999) A diagnostic fault simulator for fast diagnosis of bridge faults. Interna-
tional conference on VLSI design, pp 498-505
Wu J, Rudnick EM (Apr 2000) Bridge fault diagnosis using stuck-at fault simulation. IEEE Trans
Comput-Aided Des Integr Circuits Sys 19(4):489-495
Zou W, Cheng W-T, Reddy SM (2005) Bridge defect diagnosis with physical information. Asian
test symposium, pp 248-253
