Hardware Reference
In-Depth Information
Keshavarzi A, Roy K, Hawkins CF (1997) Intrinsic leakage in low power deep submicron CMOS
ICs. International test conference, pp 146-155
Koch B, Muller-Glaser K (1993) An examination of feedback bridging faults in digital CMOS
circuits. IEEE international symposium circuits systems, pp 1527-1530
Kruseman B, van Veen R, van Kaam K (2001) The future of delta I DDQ testing. International test
conference, pp 101-110
Kruseman B, van den Oetelaar S, Rius J (2002) Comparison of I DDQ testing and very-low voltage
testing. International test conference, pp 964-973
Kundu S (1998) I DDQ defect detection in deep submicron CMOS IC's. Asian test symposium,
pp 150-152
Khursheed S, Al-Hashimi BM, Reddy SM, Harrod P (2009) Diagnosis of multiple-voltage design
with bridge defect. IEEE Trans Comput-Aided Des 28(3):406-416
Lavo DB, Chess B, Larrabee T, Ferguson FJ, Saxen J, Butler KM (1997) Bridging fault diagnosis
in the absence of physical information. International test conference, pp 887-893
Lavo DB, Chess B, Larrabee T, Ferguson FJ (1998) Diagnosing realistic bridging faults with single
stuck-at information. IEEE Trans Comput-Aided Des 17:255-268
Levi MW (1981) CMOS is most testable. International test conference, pp 217-220
Malaya YK, Su SYH (1982) A new fault model and testing technique for CMOS devices. Interna-
tional test conference, pp 25-34
Maxwell PC, Aitken RC (1993) Biased voting: a method for simulating CMOS bridging faults in
the presence of variable gate logic thresholds. International test conference, pp 63-72
Maxwell P, O'Neill P, Aitken R, Dudley R, Jaarsma N, Quach M, Wiseman D (1999) Current ratios:
a self-scaling technique for production I DDQ testing. International test conference, pp 738-746
McCluskey EJ, Tseng C-W (2000) Stuck-fault tests vs. actual defects. International test conference,
pp 336-342
Mei KY (1974) Bridging and stuck-at faults. IEEE Trans Comput C23(7):720-727
Meijer M, Pessolano F, Pineda de Gyvez J (2004) Technology exploration for adaptive power
and frequency scaling in 90nm CMOS. International symposium on low power electronics and
design, pp 14-19
Miller AC (1999) I DDQ testing in deep submicron integrated circuits. International test conference,
pp 724-729
Millman SD, McCluskey EJ, Acken JM (1990) Diagnosing CMOS bridging faults with stuck-at
fault dictionaries. International test conference, pp 860-870
Nigh P, Forlenza D, Motika F (1997) Application and analysis of I DDQ diagnostic software. Inter-
national test conference, pp 319-327
Nigh P, Gattiker A (2004) Random and systematic defect analysis using I DDQ signature analysis
for understanding fails and guiding test decisions. International test conference, pp 309-318
Patten P (2004) Divide and conquer based fast Shmoo algorithms. International test conference,
pp 197-202
Polian I, Engelke P, Renovell M, Becker B (2003) Modeling feedback bridging faults with non-zero
resistance. European test workshop, pp 91-96
Polian I, Kundu S, Galliere J-M, Engelke P, Renovell M, Becker B (2005) Resistive bridge fault
model evolution from conventional to ultra deep submicron technologies. VLSI test sympo-
sium, pp 343-348
Pomeranz I, Reddy SM (1992) On the generation of small dictionaries for fault location. Proceed-
ings international conference on computer-aided design, pp 272-279
Rajsuman R (1991) An analysis of feedback bridging faults in MOS VLSI. VLSI test symposium,
pp 53-58
Rajsuman R (Apr 2000) I DDQ testing for CMOS VLSI. Proc IEEE 88(4):544-568
Rearick J, Patel J (1993) Fast and accurate CMOS bridging fault simulation. International test
conference, pp 54-62
Renovell M, Huc P, Bertrand Y (1994a) A unified model for inter-gate and intra-gate CMOS bridg-
ing fault: the configuration ratio. Asian test symposium, pp 170-174
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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