Models for Delay Faults - Models in Hardware Testing - page 71

scan chain failures ( Guo et al. 2006 ; Sinanoglu et al. 2007 ). This chapter contains
description of basic fault models to represent delay defects together with methods
to generate and apply tests to detect them. Some of the recent works on improving
delay defect coverage are reviewed.
In this section, fault models proposed to model the effects of delay defects and
test methods to detect the modeled faults are briefly described. In the next two sec-
tions recently developed methods to improve delay defect coverage are discussed.
Included are methods, discussed in Section 3.2 , to detect small delay defects and
coverage metrics. Another topic discussed is related to the following concern re-
garding scan based test methods. Scan allows an arbitrary state to be scanned
in. However under normal operation typically many states are not reached. Thus
scan based tests tend to operate the circuit in non-functional ways during test.
Thus scan based tests often detect many modeled faults that cannot be detected using
functionally reachable states only. Concern is that non-functional operation during
scan based tests may lead to yield loss by failing good chips ( Rearick 2001 ) . Meth-
ods to generate tests that avoid non-functional operation are discussed in Section 3.2 .
Non-functional operation leads to much higher switching activity during test caus-
ing supply voltage droops which in turn cause propagation delays in the circuit to
increase during test. Several methods to reduce switching activity during scan based
test are discussed in Chapter 7 . In Section 3.3 , DFT methods to increase delay fault
coverage and methods to reduce design effort for what is known as launch off shift
(LOS) test application method are described.

3.1.1 Basics of Test Generation

Some of the basic terms used in the context of generation of tests for digital logic
circuits and terms used in this chapter are defined and illustrated next. For simplicity
we assume that the circuits we consider contain primitive gates NOT, NOR, NAND,
OR and AND gates and flip-flops. For each gate input we ascribe two signal prop-
agation delays for propagating a falling and a rising transition from an input to the
output of a gate. For a multiple input primitive gate cv is called the controlling value
if the output of the gate is determined when one of the input value is cv. For example
0(1) is the controlling value for AND and NAND (OR and NOR) gates. Comple-
ment of the controlling value is called the non-controlling value ncv. Circuit leads
are labeled so that they can be referenced. External inputs to a circuit are called
primary inputs (PIs) and the external outputs are called primary outputs (POs). We
refer to the outputs of flip-flops driving the combinational core of a sequential cir-
cuit as pseudo-primary inputs (PPIs) and the outputs of the combinational circuit
driving the inputs of the flip-flops as pseudo-primary outputs (PPOs). A physical
path in a combinational circuit is an alternating sequence of circuit leads and is typ-
ically represented by a sequence of circuit leads such that two consecutive leads in a
path are an input and output of a gate in the circuit and the first lead in the sequence
is a PI or PPI and the last lead in the sequence is a PO or PPO. With each circuit