Hardware Reference
In-Depth Information
V
A
V
B
V
C
V
F
V
G
I
DDQ
0
0
0
0
0
Leakage
0
0
1
0
1
igh
0
1
0
0
0
Leakage
0
1
1
0
1
igh
1
0
0
0
0
Leakage
1
0
1
0
1
igh
1
1
0
1
0
igh
1
1
1
1
1
Leakage
b
c
a
V
B
V
B
V
B
V
C
V
C
V
C
V
A
V
D
V
E
V
A
V
D
V
E
V
A
V
D
V
E
R
b
R
b
R
b
gate), (
b
) both pMOS transistors on (
c
) nMOS network on (NAND gate)
I
DDQ
threshold method. Indeed, the discrimination between these two faults is pos-
sible provided that the bridged network strengths are considered (
Arumı et al.
2007
)
as shown below.
power and ground, generating thus different quiescent currents. If a set of patterns
are applied so that all the possible combinations of the bridged networks are excited,
levels are clearly observed. The lowest level corresponds to those patterns which
do not excite the bridge. The three upper levels correspond to the patterns which
activate the bridge. In these cases, apart from the leakage current, extra current is
highest current level corresponds to the case where both pMOS transistors of the
by the parallel pMOS transistors of the NAND gate, the bridge resistance and the
nMOS transistor of the inverter is lower than in the other two cases.
only two equivalent network excitations. In fact, assuming identical inverters, there
is only one different excitation. For that reason, the I
DDQ
measurements would only
show two current levels, the lowest one corresponding to the leakage current and the