Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 29

drain when the transistor was on. This transformation method was the basis for
a stuck-at fault diagnosis tool to be directly applied to the diagnosis of intra-gate
stuck-open faults.

1.5 Summary

Open defects are very common and have been studied over a wide range of CMOS
technologies. The first works were limited to stuck-open faults, which represent
only a small part of the open defects that may affect CMOS devices. For this reason,
extensive work was subsequently dedicated to the study of other classes of open
defects, such as single-floating transistors and interconnect open defects. The latter
are currently the most likely open defects to occur since interconnection structures
occupy a significant part of the total area of VLSI chips.
Process variations and partial opens have an increasing impact on nanometer
technologies, consequently resistive opens have dominated most research during
the last years. The continuous CMOS scaling trend causes new failure mechanisms.
Among these, the influence of leakage currents on the behavior of open defects has
opened a new field of research, which is expected to contribute new techniques for
test and diagnosis of these defects.

References

Aitken RC (2002) Test generation and fault modeling for stress testing. International symposium
on quality electronic design, pp 95-99
Arumı D, Rodrıguez-Monta nes R, Figueras J (May 2005) Defective behaviours of resistive opens
in interconnect lines. European test symposium, pp 28-33
Arumı D, Rodrıguez-Monta nes R, Figueras J (Jan 2008a) Experimental characterization of CMOS
interconnect open defects. IEEE Trans Comput-Aided Des Integr Circuits Sys 27(1):123-136
Arumı D, Rodrıguez-Monta nes R, Figueras J, Eichenberger S, Hora C, Kruseman B (2008b) Full
open defects in nanometric CMOS. VLSI test symposium, pp 119-124
Arumı D, Rodrıguez-Monta nes R, Figueras J (2008c) Delay caused by resistive opens

in interconnecting lines, accepted for publication in Integration, the VLSI Journal,

http://dx.doi.org/10.1016/j.vlsi.2008.11.001
Baker K, Gronthoud G, Lousberg M, Schanstra I, Hawkins C (1999) Defect-based delay testing of
resistive vias contacts: a critical evaluation. International test conference, pp 467-476
Champac VH, Rubio A, Figueras J (1993) Analysis of the floating gate defect in CMOS. Defect
and fault tolerance in VLSI systems, pp 101-108
Champac VH, Rubio A, Figueras J (Mar 1994) Electrical model of the floating gate defect in
CMOS ICs: implications on I DDQ testing. IEEE Trans Comput-Aided Des Integr Circuits Syst
13(3):359-369
Champac VH, Zenteno A (2000) Detectability conditions for interconnection open defects. VLSI
test symposium, pp 305-311
Chang JTY, McCluskey EJ (1997) SHOrt Voltage Elevation (SHOVE) test for weak CMOS ICs.
VLSI test symposium, pp 446-451