Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 28

Fig. 1.26 Resistive open
faults in a NAND gate

R 3 R 2

R 10

R 11

R 13

R 7 R 6

B

Z

R 5 R 14

R 12

R 9

A

R 4

R 8

R 1

a

D

b

S

D SG

G

G

D

S

G S D

S G1 S G2

c d D S

G1 G2

G1 G2

S G1 S G2 S D D

Fig. 1.27 Gate level equivalences ( Fan et al. 2005 ) . ( a ) n-transistor, ( b ) p-transistor, ( c ) parallel
n-transistors, and ( d ) parallel p-transistors

modeled as the combination of two transition faults. The proposed technique uses a
stuck-at fault diagnosis as a first step. In the second step, excitation condition tables
are built for every gate and resistive open to find the fault gate input sequence.

1.4.2 Diagnosis of Intra-gate Open Defects

Stuck-open fault diagnosis has also been investigated. In the work by Li and
McCluskey ( 2002 ), two tables were built for every type of gate. The first contained
the gate input pair to excite stuck-open faults. The second listed input values of the
gates for every test pattern applied on the tester. With this information, the possible
sequence behavior of stuck-open defects was considered during diagnosis.
In the proposal by Fan et al. ( 2005 ), a transformation method was developed
where transistors were replaced by a gate-level equivalent so that a stuck-open fault
was represented with a stuck-at fault, as described in Fig. 1.27 . For n-transistors
(p-transistors), the idea was to propagate the 0 (1) voltage from the source to the