Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 25

lower (higher) than the threshold voltage of the downstream gate. Assuming that
E. 0 / D Œmin E.p/; max E.p/ for 8 p 2 0 and E. 1 / D Œmin E.p/; max E.p/
for 8 p 2 1 , to obtain consistent results in the presence of an open defect, Eq. 1.10
should be satisfied.

E. 0 /<E. 1 / (1.10)

This methodology neglected capacitances between internal nodes. Its feasibility was
also limited in situations where the floating net had fan-out and the threshold volt-
ages of the inputs of the driven gates were different, since Eq. 1.10 may not be
satisfied. Furthermore, this work focused on open vias only and discarded finding
opens due to broken metal tracks.
The diagnosis technique presented by Zou et al. ( 2006 ) was founded on the seg-
ment fault model previously proposed by Huang ( 2002 ) . In this methodology, the
segment model was used as a first step to get the set of potential open segments re-
sponsible for the faulty behavior. Subsequently, SPICE simulations were carried out
to calculate the input threshold voltages of the driven gates. With all this information
and the charge conservation principle, a prediction of the initial trapped charge was
made. According to the above principle, once the initial charge is trapped in the
circuit during the fabrication process, the total amount of charge does not change
and is redistributed among the capacitors when different test patterns are applied, as
described by Eq. 1.11 :

Q trap D Q wire P; V fn C Q gate V fn

(1.11)

where Q wire .P; V fn / is the sum of charges stored in the capacitors between the float-
ing node and its coupled neighbors. This factor depends on the test pattern applied
(P) and the floating node voltage .V fn /.Q gate .V fn / is the charge stored in the ca-
pacitors of the downstream gates and it also depends on the floating node voltage
.V fn /. For a set of test patterns, it was possible to determine an upper and lower
bound for the Q trap value. The consistency of these results was used to reduce the
number of possible open vias within the segments explaining the faulty behavior.
The application of such methodology requires the use of Q-V look-up tables for
every gate.
In the proposal of Rodrıguez-Montanes et al. ( 2007a ) , the target net was divided
according to the FOS (Full Open Segment) model to diagnose interconnect full open
defects in long floating lines where the impact of transistor capacitances are low. The
FOS model considered any possible location of the open along the line. With this
model, the floating line is partitioned into several segments (Seg i). Segment breaks
are caused by a change in the neighborhood layout. For the example in Fig. 1.24 , the
target line is divided into nine different segments. Hence, each segment consists of
the target line and zero to two neighboring lines since only coupling neighbors be-
tween the same metal layer are considered. It is therefore possible to extract the
parasitic capacitances for every segment easily. Given an open location (segment k)
and a test pattern (P), the floating line voltage is determined by the parasitic capaci-
tances of the segments located after the open, as reported in Eq. 1.12 .