Hardware Reference
In-Depth Information
transistors were in the off state, it was possible to detect the defect by capturing an
intermediate voltage at the floating node due to hazards that may affect the CMOS
network. Finally, open O
3
was the most difficult to detect by current testing because
this class of faults usually had a stuck-at behavior.
additional information about open defects. Some defective devices showed time-
dependent I
DDQ
behavior with evolution in the order of seconds. The authors
conjectured that this dynamic behavior could be associated with an open defect and
the subthreshold, gate and reverse bias pn junction leakage currents flowing into and
out of the affected node.
1.4
Diagnosis of Open Defects
Accurate diagnosis of failure sites is important for solving process problems, ana-
lyzing failures and improving yields. The current diagnosis effort related to open
defects has focused mostly on interconnect opens. Accordingly, in this section
we will first analyze the strategies to diagnose interconnect opens followed by an
overview of the techniques used to diagnose intra-gate opens.
1.4.1
Diagnosis of Interconnect Open Defects
One of the first works on diagnosis of interconnect open defects was conducted
by
Venkataraman and Drummonds
(
2000
). The proposed methodology was based
on logic information using the net diagnostic model. This model takes the differ-
ent branches of the defective line into account. Let us now look at the example in
caused by a 0/1 error at locations A, B and C are saved in the erroneous observation
errors caused by a 1/0 error are saved in the sets EO
2
,EO
4
and EO
6
, respectively.
The diagnostic signature EO for stem A is then computed as the union of sets EO
1
,
EO
2
,EO
3
,EO
4
,EO
5
and EO
6
. In the presence of an open on net ABC, only a sub-
set of set EO is faulty. A path-tracing procedure can be used to identify the logic
nets potentially associated with an interconnect open.
A
B
C
