Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 22

1.3.2.3 Alternative Techniques for the Detectability of Intra-gate

Open Defects

The modification of power supply voltage can also be useful for detecting intra-gate
opens. Li et al. ( 2001 ) provided simulations where a resistive open was injected into
the gate delay path of an inverter chain. The results showed that this class of fault
was more easily detected at low power supply voltages. Furthermore, as previously
reported, the delay added by transistor-related defects increased non-linearly when
the power supply value was decreased. This behavior occurs when these transistor-
related defects are due to intra-gate opens ( Yan and Singh 2005 ).
I DDQ testing is another alternative for detecting intra-gate opens for technologies
with low background leakage currents. However, even in these technologies, the ef-
ficiency of I DDQ testing is strongly dependent on cell design, circuit topology and
open location. For example, the work by Champac et al. ( 1994 )presentedtheI DDQ
detectability of a single floating transistor. It was reported that the location of the
poly-break, modeled by the poly-bulk and metal-poly capacitances, determined the
degree of conduction of the floating gate transistor and its detectability by current
testing. For sufficiently high values of the poly-bulk capacitance, the defective tran-
sistor may work in the subthreshold region, where it can be modeled as a stuck-open
transistor. It is therefore not detectable by an I DDQ test. However, for sufficiently low
values of the poly-bulk capacitance and sufficient metal track influence, the floating
gate transistor operated above threshold, generating non-negligible I DDQ values.
Singh et al. ( 1995 ) reported the results of an experimental test chip for analyzing
the I DDQ detectability of open defects. Open faults were divided into five different
groups, see Fig. 1.21 , namely open disconnecting a transistor pair .O 1 /, a single
floating net belonging to a transistor being the only conduction path to the power
rails .O 2 /, an open source/drain on the only conduction path to the power rails .O 3 /,
a floating gate in a transistor on one of multiple conduction paths to V DD or GND
.O 4 /, and finally an open source/drain on one of multiple conduction paths to V DD
or GND .O 5 /. Based on the experimental results, the authors reported that opens O 1
and O 2 were the most likely to be detected by a I DDQ test although their detectability
could not be ensured for all configurations. For opens O 4

and O 5 , if the affected

O 5

O 4

O 1

A

Z

O 2

B

O 3

Fig. 1.21 I DDQ detectability
of open defects ( Singh
et al. 1995 )