Hardware Reference
In-Depth Information
Tabl e 1. 2
Test sequences for the gate in Fig. 1.14 (Di and Jess 1993)
Test 1
Pattern
A
B
C
D
E
Z (fault-free)
Z (faulty)
1
1
0
1
0
1
1
1
2
1
0
1
1
0
0
1
Test 2
3
1
1
1
0
0
0
0
4
1
1
0
0
1
1
1
5
1
1
0
0
0
0
1
input E changes. To overcome such problems,
Di and Jess
(
1993
) proposed a fault
model considered at logic level. Detectability conditions were derived from Reduced
Ordered Binary Decision Diagrams (ROBDD) data structures used during fault sim-
ulation. To avoid hazard effects, the two test sequences were chosen such that during
the transition from the initialization phase to the test phase there was no temporary
leakage path draining the charged output. In case of charge-sharing effects, a local
circuit analysis was performed to estimate the voltage level after charge-sharing to
check the validity of the test sequence. During the initialization phase, the charge-
sharing path was set to conduct so that all nodes on the charge-sharing path were
charged to a voltage level equal to that of the output node.
nections were taken into account without any knowledge about the circuit layout.
The conditions of a node break fault were derived from electrical considerations.
The minimum number of patterns needed to test the fault was determined based on
graph theory. Testing a node-break fault is an implicit test for stuck-open faults of
every transistor whose drain or source is connected to that node.
1.3
Detectability of Open Defects
This section briefly presents the different methodologies to improve the detectability
of open defects, following the classification based on defect location.
1.3.1
Detectability of Interconnect Open Defects
Logic-based methodologies are the most commonly used techniques for the detec-
tion of interconnect open defects. However, they are not always effective. Thereby,
other alternatives have been developed to improve or complement the success of
logic-based techniques. They are all summarized in the following subsections.
