Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 16

1.3.1.1 Logic Detectability of Interconnect Open Defects

In the presence of an interconnect full open, the floating line voltage is basically
determined by the ratio between the parasitic capacitances related to the floating
line tied to V DD .C UP / and the sum of all the parasitic capacitances .C UP C C DOWN /

plus the influence of the trapped charge V Qo , as previously reported in Eq. 1.5 . On
the one hand, the trapped charge is an unknown but constant parameter. On the other
hand, the ratio between the parasitic capacitances tied to V DD and the total parasitic
capacitance depends on a number of factors. One is the relationship between tran-
sistor and neighboring capacitances. When the floating line length .L FL / is short,
transistor capacitances generally dominate and set the floating line to an interme-
diate value. Nevertheless, for long L FL , neighboring capacitances dominate and the
floating line may achieve a wider range of values. The exact location of the open
is also important since only parasitic capacitances located after the open influence
the floating line. The last factor is the test pattern applied because it sets a certain
state on the neighboring lines. Champac and Zenteno ( 2000 ) presented simulation
results showing the influence of these factors. Furthermore, experimental evidence
was provided in the work by Arum´ıetal. ( 2008a ) , where a set of open defects was
intentionally injected into a test circuit. Every floating line was routed between two
neighboring lines with different coupling lengths. Experimental results showed that
when both neighbors had the same logic value, they determined the logic interpre-
tation of the floating line, even for floating lines of a few tens of m in length.
Therefore, in the presence of an interconnect full open defect, its detectability
when carrying out a logic test can be improved in the following manner:

Testing for an SA1 at the target node: Maximize the C UP =.C UP C C DOWN / ratio.

Testing for an SA0 at the target node: Minimize the C UP =.C UP C C DOWN / ratio.

1.3.1.2 Delay Detectability of Interconnect Open Defects

In general, resistive defects have an impact on the time response of the circuit.
Hence, delay testing is a widely used technique to detect such defects, including
resistive opens. In the presence of an interconnect resistive open, signals propagated
through the defective line undergo an extra delay. If the sum of the defect-free delay
plus the one added by the defect exceeds the maximum delay permitted (test period),
a malfunction can be caused and the defect is detected ( Li et al. 2001 ; Kruseman
and Heiligers 2006 ) . However, performing a delay test at nominal conditions (speed)
may lead to missing resistive opens. If the defect is sensitized along a short path,
then the total delay may not exceed the maximum permitted. Nevertheless, if the
defect were sensitized along a longer path, it could be detected. Therefore, the sen-
sitization path is a key factor to detect resistive opens.
The other important factor is the open resistance. The higher the resistance, the
larger the delay. Thus, given a fault site (location) and a test pattern (sensitization
path), it is possible to predict the critical resistance, i.e., the minimum open resis-
tance which generates sufficient delay so that a faulty behavior is observed. Baker