Hardware Reference
In-Depth Information
a
b
D
c
D
d
Drain (D)
C
1
C
1
C
1
C
1
C
2
C
2
C
2
C
2
B
ulk
(B)
Gate
(G)
G
B
BG
B
C
4
C
4
C
4
C
4
C
3
C
3
C
3
C
3
C
gb
C
gb
C
gb
C
gb
Source (S)
S
S
Fig. 1.15
nMOS transistor model (
Maly et al.
1991
). (
a
) Fault free, (
b
) open gate, (
c
) open source,
and (
d
) open drain
Fig. 1.16
Example of an
intra-gate open fault
D
C
E
A
B
Z
A
D
B
E
C
might be generated in the high impedance state. Although widely used, stuck-open
faults only cover a small fraction of faults caused by actual opens. In this sense, in
the work by
Maly et al.
(
1991
), the analysis of
full
opens was extended to faults
located in any of the transistor terminals, as described in Fig.
1.15
for an nMOS
transistor.
These previous models are not robust because they ignore both hazards and
charge-sharing effects. In order to evaluate the impact of these effects, let us consider
the example in Fig.
1.16
and the sequence of patterns in Table
1.2
(
Di and Jess
1993
)
.
If Test 1 is applied to the circuit, the output (Z) is charged to V
DD
and subsequently
set to a high impedance state. With this sequence, the open could be detected. How-
ever, if some delay forces input D to change earlier than input E, a temporary leakage
path from Z to GND is generated. Output Z can then be discharged, invalidating the
test. This problem can be solved by applying a test sequence like Test 2, where only
