Open Defects in Nanometer Technologies Models, Test and Diagnosis - Models in Hardware Testing - page 13

1.2.2 Intra-gate Open Defects

The first research on open defects addressed the effect of stuck-open faults in CMOS
circuits. The stuck-open fault model ( Wadsack 1978 ) is a failure mechanism mod-
eled as a loss of charge transfer in one transistor of the defective cell or gate so
that the output is set to a high impedance state for at least one logic state. Thus, a
sequential behavior is observed at the output node depending on its previous logic
state. Figure 1.14 illustrates a 2-input NAND gate where the source terminal of one
of the pMOS transistors is disconnected from the output. For the state (A B) = (1 0),
the output (Z) is in a high impedance state. Hence, if the previous pattern applied
is (A B) = (1 1), Z is interpreted as logic 0; otherwise it is interpreted as logic 1, as
reported in Table 1.1 .
Initial work on full opens disconnecting one single gate transistor terminal (Float-
ing Gate Open) was carried out by Renovell and Cambon ( 1986 , 1992 ). Champac
et al. ( 1993 , 1994 ) modeled this defect and validated the proposed model by ex-
periments on test chips designed with intentional open defects. The floating gate
voltage depends on the location of the poly break, modeled by the poly-bulk and
metal-poly capacitances. The affected transistor may operate in the sub-threshold
region, behaving as a stuck-open transistor or operate in the saturation and ohmic
regions.
In the work by Soden et al. ( 1989 ), experiments were conducted to evaluate the
transient response and current behavior of stuck-open faults. The results corrob-
orated the predicted sequential behavior. Furthermore, high current consumption

A

Z

B

Fig. 1.14 Stuck-open fault in
a NAND gate

Tabl e 1. 1 Stuck open
behavior in a NAND gate

Input port (A) Input port (B) Output port (Z)

0 0 1

0 1 1

1 0 High impedance

1 1 0