Physical Fault Models and Fault Tolerance - Models in Hardware Testing - page 225

between blocks with a relatively regular layout, such as programmable logic arrays
(PLA), and blocks with a random layout.
For PLAs, due to the array nature, the gate arrangement is fixed and concurs
with all the layout rules that we have defined. For such blocks, it is therefore easy
to determine test sequences with satisfactory fault coverage.
The situation is more difficult for random logic. Although it is always feasible
to apply all rules, the relative freedom offered by some of them means that, for a
given function, several possible layouts are possible, each with different area. De-
termining the minimal one is therefore a complex task. In the years when the work
was conducted, no design tools able to provide an automatic solution to such an
optimization problem were available, and the search for a solution was essentially
based on designer's skills. Thus, to reduce the design periods required for a circuit,
two methods can be retained, depending on the nature of the block. For the specific
blocks appearing only on one particular chip (custom design), one can systemat-
ically apply all layout rules without optimization. Conversely, for the basic blocks
appearing on many chips (flip-flops, registers, counters, RAM, etc.), an optimization
can lead to a block library that will then be used by the designer for future circuits.
These general remarks can be illustrated by a particular block in the applica-
tion circuit: a master-slave flip-flop used in the realization of registers or counters.
Because at that time, conventional layout rules did not consider testing require-
ments, no preestablished test sequence can be formed for 30% of the shorts between
two metallizations and for 28% of the shorts between two diffusions. This situation
arises from the fact that these defects introduce analog behaviors. Systematic ap-
plication of all layout rules leads to a design for which all shorts and opens can be
detected by a very simple test sequence (Set-Reset-Set), but with an area increase
of 30% after optimization.
This area increase does not, however, apply to the whole circuit because at a
chip level we have to account for the following factors: (1) the I/O buffers and
the interconnections take up a non negligible area which is not influenced by the
application of these rules, and (2) certain blocks (e.g., PLA) have an arrangement
such that the respect of the layout rules leads to a very slight or even negligible
increase.

8.2.4 Modeling of Errors Induced in Operation

We now address defects acting during the operation of the chip. In this case, the
single defect assumption is a realistic one. Thus, we focus on studying, in isolation,
the error induced by each type of defect, such as: shorts, opens, threshold voltage
drift and degradation of propagation time.
As previously depicted by Fig. 8.3 a , a MOS single channel gate can be repre-
sented by a load transistor and a switch-like network arranged between the two
power supply lines: V DD and V SS .