Physical Fault Models and Fault Tolerance - Models in Hardware Testing - page 224

8.2.3.3 Test Strategies

According to whole set of rules that has been defined, two different test strategies
can be considered:

S1 Apply only the layout rules related to the arrangement of the gates.

In this case, the possible defects of a block are: (1) shorts and opens inside the gates
that cannot all be modeled by stuck-at faults, (2) opens of gate interconnections that
can all be modeled as stuck-at faults, and (3) shorts between two gate interconnec-
tions that cannot induce asynchronous sequential loops and can be modeled by OR
wiring of the two shorted connections.
The determination of a test sequence for the whole block can thus be divided into
three steps:

1. Determine a complete test sequence for each gate of the block with the method
described in Section 8.2.2.2 using the transistor diagram of this gate.
2. Determine a test sequence at the level of the whole block, applying to each gate
its own test sequence. This can be done by using a path sensitization method on
the logic diagram of the block. Notice that this sequence also detects all inter-
connection opens.
3. The test sequence obtained after step 2 will generally also detect some shorts
between interconnections. For each undetected short, a specific test vector must
be added to that sequence. Using the logic diagram of the block, this test vector
can be derived by first setting anyone of the shorted interconnections at logical
state 0, the other at logical state 1, and then propagating the logical state of the
latter interconnection to an observable output of the block.

S2 Apply all rules concerning both the arrangement of the gates and the arrange-

ment of the connections inside the gates.

The main difference with respect to S1 is that all shorts and opens inside the
gates can be modeled by stuck-at faults. This offers the advantage of saving step 1
in the previous testing procedure, thus reducing computation time and avoiding the
need for the transistor diagram. Generating a test sequence for S2 can therefore be
achieved simply in two steps:

1. Determination on the logic diagram of a test sequence for stuck-at faults of the
connections of that diagram.
2. Same as step 3 for S1 .

8.2.3.4 Application

The application of these layout rules involves, for a given function, an increase of
the chip area. To evaluate this approach, these layout rules were applied to a set
of basic building blocks of the application circuit. There is a significant difference