Hardware Reference
In-Depth Information
8.2.4.1
Shorts
Each short that can affect the switch-like network (including the output connection)
increases the number of conduction paths and thus creates an error at 0 of the output
of the gate. This error is transient or permanent depending whether the short is
resistive or not. The error is of the single type if the short does not affect more than
two gates. It is unidirectional if it affects more than two gates. A short of the load
transistor decreases the load resistance and degrades the logical level 0 which in turn
may produce a transient or permanent error at 1 whether the short is clean or not.
8.2.4.2
Opens
An open provokes a dual effect when compared to a short. Thus, an open in the
switch-like network leads to a permanent error at 1 and an open of the load transistor
leads to a permanent error at 0.
An open of a connection between gates leads to a floating potential on the gates
of the control transistors located below; the induced transient error is unidirectional
if the cut connection is a divergent one.
Opens of the supply lines V
DD
or V
SS
lead respectively to a permanent stuck-
at-0 (s-a-0) or stuck-at-1 (s-a-1) of the outputs of the gates and give a permanent
unidirectional error at 0 or 1.
8.2.4.3
Threshold Voltage Drift
A threshold voltage drift renders any action on the transistor gate ineffective. The
error induced by this fault is a 0 or 1 error whether the threshold voltage is decreased
or increased. Such a kind of fault can simultaneously affect several transistors in the
same way and thus can create a single (or unidirectional) error(s) depending whether
the transistors belong to the same gate or not.
Such faults can be due to external disturbances such as temperature or power
supply variations. In this case, the resulting error is transient and its duration is
equal to the duration of the external disturbance.
8.2.4.4
Degradation of Propagation Time
As for the threshold voltage drift, the degradation of the propagation time can affect
several transistors and can be induced by external phenomena. The main difference
is that the error in this case depends on the variable generated by the faulted gate.
This error multiple if the gates impacted by the failure generate complementary
logic variables.
