Physical Fault Models and Fault Tolerance - Models in Hardware Testing - page 218

8.2.2.2 Test Sequence Generation at the Gate Level

For testing at the gate level, we first need to define the notion of a conduction path
that will be used later. MOS technology enables the realization of complex gates in-
cluding several cascaded AND/OR basic functions (Fig. 8.3 a ). Schematically, such a
gate can be divided into two parts: a load transistor and a set of “control” transistors
that can be considered as a switch-like network.
The switch-like network constitutes the active part of the gate. It allows, by
applying convenient input patterns, the realization of a set of conduction paths
between the output node and the V SS power supply node. A conduction path is
activated when all of its control transistors are on. Conversely, a conduction path is
blocked when at least one of its control transistors is off. For the whole gate, when
one (or more) paths between the output node and the V SS node is (are) activated, the
output of the gate is at V SS , i.e., logical state 0, while, when all conduction paths are
blocked, the output of the gate is at V DD , i.e., logical state 1.
Opens Depending on its location, an open in the switch-like network corresponds
to the removal of one or more conduction paths. In order to detect such an open, two
conditions are required: (1) activate at least one of the conduction paths between
the output node and the V SS node which connects to the open line, and (2) block all
the conduction paths between the output node and the V SS node not connected to
the open line.
When these conditions are fulfilled, if the considered open is not present, at least
one conduction path is really activated and the output of the gate is at logical state 0.
Otherwise, if this open is present, no conduction path is activated and the output
of the gate remains at logical state 1. The potential presence of the open is indeed
observed at the output of the gate.
In order to derive a test sequence able to detect all possible opens in the switch-
like network, a systematic procedure deduced from the general graph theory is given
in Galiay ( 1978 ). It consists of first listing all the conduction paths between the out-
put node and the V SS node and then successively activating one of these conduction
paths and simultaneously blocking all the others. For example, Table 8.2 gives a set
of five test vectors obtained for the gate of Fig. 8.3 a .
The test sequence obtained with such a systematic procedure is generally redun-
dant, but minimizing its length is only feasible if we have information about the
actual layout of the control transistors. For instance, if the layout is exactly the one
of Fig. 8.3 a , only the three tests T2, T3, and T5 are required to detect all opens in
the switch-like network.

Tabl e 8. 2 Test sequence for
opens in gate of Fig. 8.3 a

abcdef Activedpath

T1 10100- ac

T2 10010- ad

T3 01100- bc

T4 01010- bd

T5 00--11 ef